Merge phase #3 (IOMMU) of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-v28-for-linus-phase3-B' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (74 commits) AMD IOMMU: use iommu_device_max_index, fix AMD IOMMU: use iommu_device_max_index x86: add PCI IDs for AMD Barcelona PCI devices x86/iommu: use __GFP_ZERO instead of memset for GART x86/iommu: convert GART need_flush to bool x86/iommu: make GART driver checkpatch clean x86 gart: remove unnecessary initialization x86: restore old GART alloc_coherent behavior revert "x86: make GART to respect device's dma_mask about virtual mappings" x86: export pci-nommu's alloc_coherent iommu: remove fullflush and nofullflush in IOMMU generic option x86: remove set_bit_string() iommu: export iommu_area_reserve helper function AMD IOMMU: use coherent_dma_mask in alloc_coherent add AMD IOMMU tree to MAINTAINERS file AMD IOMMU: use cmd_buf_size when freeing the command buffer AMD IOMMU: calculate IVHD size with a function AMD IOMMU: remove unnecessary cast to u64 in the init code AMD IOMMU: free domain bitmap with its allocation order AMD IOMMU: simplify dma_mask_to_pages ...
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@@ -48,6 +48,11 @@ static inline int is_device_dma_capable(struct device *dev)
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return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
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}
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static inline int is_buffer_dma_capable(u64 mask, dma_addr_t addr, size_t size)
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{
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return addr + size <= mask;
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}
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#ifdef CONFIG_HAS_DMA
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#include <asm/dma-mapping.h>
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#else
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@@ -58,6 +63,13 @@ static inline int is_device_dma_capable(struct device *dev)
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#define dma_sync_single dma_sync_single_for_cpu
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#define dma_sync_sg dma_sync_sg_for_cpu
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static inline u64 dma_get_mask(struct device *dev)
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{
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if (dev && dev->dma_mask && *dev->dma_mask)
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return *dev->dma_mask;
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return DMA_32BIT_MASK;
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}
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extern u64 dma_get_required_mask(struct device *dev);
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static inline unsigned int dma_get_max_seg_size(struct device *dev)
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@@ -1,6 +1,20 @@
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#ifndef _LINUX_IOMMU_HELPER_H
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#define _LINUX_IOMMU_HELPER_H
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static inline unsigned long iommu_device_max_index(unsigned long size,
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unsigned long offset,
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u64 dma_mask)
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{
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if (size + offset > dma_mask)
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return dma_mask - offset + 1;
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else
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return size;
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}
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extern int iommu_is_span_boundary(unsigned int index, unsigned int nr,
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unsigned long shift,
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unsigned long boundary_size);
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extern void iommu_area_reserve(unsigned long *map, unsigned long i, int len);
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extern unsigned long iommu_area_alloc(unsigned long *map, unsigned long size,
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unsigned long start, unsigned int nr,
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unsigned long shift,
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@@ -8,3 +22,5 @@ extern unsigned long iommu_area_alloc(unsigned long *map, unsigned long size,
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unsigned long align_mask);
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extern void iommu_area_free(unsigned long *map, unsigned long start,
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unsigned int nr);
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#endif
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@@ -497,6 +497,16 @@
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#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP 0x1101
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#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL 0x1102
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#define PCI_DEVICE_ID_AMD_K8_NB_MISC 0x1103
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#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
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#define PCI_DEVICE_ID_AMD_10H_NB_MAP 0x1201
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#define PCI_DEVICE_ID_AMD_10H_NB_DRAM 0x1202
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#define PCI_DEVICE_ID_AMD_10H_NB_MISC 0x1203
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#define PCI_DEVICE_ID_AMD_10H_NB_LINK 0x1204
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#define PCI_DEVICE_ID_AMD_11H_NB_HT 0x1300
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#define PCI_DEVICE_ID_AMD_11H_NB_MAP 0x1301
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#define PCI_DEVICE_ID_AMD_11H_NB_DRAM 0x1302
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#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
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#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
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#define PCI_DEVICE_ID_AMD_LANCE 0x2000
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#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
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#define PCI_DEVICE_ID_AMD_SCSI 0x2020
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