Merge branch 'linus' into x86/urgent
Merge reason: Bring in changes that the next patch will depend on. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
@@ -17,6 +17,8 @@
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#include <asm/time.h>
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#include <asm/delay.h>
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#include <asm/hypervisor.h>
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#include <asm/nmi.h>
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#include <asm/x86_init.h>
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unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
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EXPORT_SYMBOL(cpu_khz);
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@@ -400,15 +402,9 @@ unsigned long native_calibrate_tsc(void)
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{
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u64 tsc1, tsc2, delta, ref1, ref2;
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unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
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unsigned long flags, latch, ms, fast_calibrate, hv_tsc_khz;
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unsigned long flags, latch, ms, fast_calibrate;
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int hpet = is_hpet_enabled(), i, loopmin;
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hv_tsc_khz = get_hypervisor_tsc_freq();
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if (hv_tsc_khz) {
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printk(KERN_INFO "TSC: Frequency read from the hypervisor\n");
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return hv_tsc_khz;
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}
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local_irq_save(flags);
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fast_calibrate = quick_pit_calibrate();
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local_irq_restore(flags);
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@@ -566,7 +562,7 @@ int recalibrate_cpu_khz(void)
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unsigned long cpu_khz_old = cpu_khz;
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if (cpu_has_tsc) {
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tsc_khz = calibrate_tsc();
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tsc_khz = x86_platform.calibrate_tsc();
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cpu_khz = tsc_khz;
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cpu_data(0).loops_per_jiffy =
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cpufreq_scale(cpu_data(0).loops_per_jiffy,
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@@ -744,10 +740,16 @@ static cycle_t __vsyscall_fn vread_tsc(void)
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}
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#endif
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static void resume_tsc(void)
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{
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clocksource_tsc.cycle_last = 0;
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}
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static struct clocksource clocksource_tsc = {
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.name = "tsc",
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.rating = 300,
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.read = read_tsc,
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.resume = resume_tsc,
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.mask = CLOCKSOURCE_MASK(64),
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.shift = 22,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS |
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@@ -761,12 +763,14 @@ void mark_tsc_unstable(char *reason)
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{
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if (!tsc_unstable) {
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tsc_unstable = 1;
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printk("Marking TSC unstable due to %s\n", reason);
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printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
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/* Change only the rating, when not registered */
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if (clocksource_tsc.mult)
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clocksource_change_rating(&clocksource_tsc, 0);
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else
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clocksource_mark_unstable(&clocksource_tsc);
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else {
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clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
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clocksource_tsc.rating = 0;
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}
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}
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}
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@@ -852,15 +856,71 @@ static void __init init_tsc_clocksource(void)
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clocksource_register(&clocksource_tsc);
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}
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#ifdef CONFIG_X86_64
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/*
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* calibrate_cpu is used on systems with fixed rate TSCs to determine
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* processor frequency
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*/
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#define TICK_COUNT 100000000
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static unsigned long __init calibrate_cpu(void)
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{
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int tsc_start, tsc_now;
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int i, no_ctr_free;
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unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0;
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unsigned long flags;
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for (i = 0; i < 4; i++)
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if (avail_to_resrv_perfctr_nmi_bit(i))
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break;
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no_ctr_free = (i == 4);
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if (no_ctr_free) {
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WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... "
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"cpu_khz value may be incorrect.\n");
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i = 3;
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rdmsrl(MSR_K7_EVNTSEL3, evntsel3);
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wrmsrl(MSR_K7_EVNTSEL3, 0);
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rdmsrl(MSR_K7_PERFCTR3, pmc3);
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} else {
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reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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local_irq_save(flags);
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/* start measuring cycles, incrementing from 0 */
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wrmsrl(MSR_K7_PERFCTR0 + i, 0);
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wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
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rdtscl(tsc_start);
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do {
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rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now);
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tsc_now = get_cycles();
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} while ((tsc_now - tsc_start) < TICK_COUNT);
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local_irq_restore(flags);
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if (no_ctr_free) {
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wrmsrl(MSR_K7_EVNTSEL3, 0);
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wrmsrl(MSR_K7_PERFCTR3, pmc3);
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wrmsrl(MSR_K7_EVNTSEL3, evntsel3);
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} else {
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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return pmc_now * tsc_khz / (tsc_now - tsc_start);
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}
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#else
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static inline unsigned long calibrate_cpu(void) { return cpu_khz; }
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#endif
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void __init tsc_init(void)
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{
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u64 lpj;
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int cpu;
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x86_init.timers.tsc_pre_init();
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if (!cpu_has_tsc)
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return;
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tsc_khz = calibrate_tsc();
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tsc_khz = x86_platform.calibrate_tsc();
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cpu_khz = tsc_khz;
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if (!tsc_khz) {
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@@ -868,11 +928,9 @@ void __init tsc_init(void)
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return;
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}
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#ifdef CONFIG_X86_64
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if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
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(boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
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cpu_khz = calibrate_cpu();
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#endif
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printk("Detected %lu.%03lu MHz processor.\n",
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(unsigned long)cpu_khz / 1000,
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