Merge branch 'orion' into devel
* orion: (26 commits) [ARM] Orion: implement power-off method for QNAP TS-109/209 [ARM] Orion: add support for QNAP TS-109/TS-209 [ARM] Orion: I2C support [I2C] i2c-mv64xxx: Don't set i2c_adapter.retries [I2C] Split mv643xx I2C platform support [ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323 [ARM] Orion defconfig [ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323 [ARM] Orion: MV88F5181 support bits [ARM] Orion: Buffalo/Revogear Kurobox Pro support [ARM] OrionNAS RD board support [ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board [ARM] Orion: common platform setup for Gigabit Ethernet port [ARM] Orion: platform device registration for UART, USB and NAND [ARM] Orion: system timer support [ARM] Orion edge GPIO IRQ support [ARM] Orion: IRQ support [ARM] Orion: provide GPIO method for enabling hardware assisted blinking [ARM] Orion: GPIO support [ARM] Orion: programable address map support ... Conflicts: arch/arm/Kconfig arch/arm/Makefile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Russell King
@@ -342,6 +342,27 @@ config CPU_XSC3
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select CPU_TLB_V4WBI if MMU
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select IO_36
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# Feroceon
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config CPU_FEROCEON
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bool
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depends on ARCH_ORION
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default y
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_CP15_MMU
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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config CPU_FEROCEON_OLD_ID
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bool "Accept early Feroceon cores with an ARM926 ID"
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depends on CPU_FEROCEON && !CPU_ARM926T
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default y
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help
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This enables the usage of some old Feroceon cores
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for which the CPU ID is equal to the ARM926 ID.
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Relevant for Feroceon-1850 and early Feroceon-2850.
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# ARMv6
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config CPU_V6
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bool "Support ARM V6 processor"
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@@ -539,7 +560,7 @@ comment "Processor Features"
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config ARM_THUMB
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bool "Support Thumb user binaries"
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depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7
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depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
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default y
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help
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Say Y if you want to include kernel support for running user space
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@@ -601,7 +622,7 @@ config CPU_DCACHE_SIZE
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config CPU_DCACHE_WRITETHROUGH
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bool "Force write through D-cache"
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depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
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depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE
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default y if CPU_ARM925T
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help
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Say Y here to use the data cache in writethrough mode. Unless you
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@@ -68,6 +68,7 @@ obj-$(CONFIG_CPU_SA110) += proc-sa110.o
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obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o
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obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o
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obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o
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obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o
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obj-$(CONFIG_CPU_V6) += proc-v6.o
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obj-$(CONFIG_CPU_V7) += proc-v7.o
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506
arch/arm/mm/proc-feroceon.S
Normal file
506
arch/arm/mm/proc-feroceon.S
Normal file
@@ -0,0 +1,506 @@
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/*
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* linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
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*
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* Heavily based on proc-arm926.S
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* Maintainer: Assaf Hoffman <hoffman@marvell.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/elf.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define CACHE_DLIMIT 16384
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/*
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* the cache line size of the I and D cache
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*/
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#define CACHE_DLINESIZE 32
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.text
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/*
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* cpu_feroceon_proc_init()
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*/
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ENTRY(cpu_feroceon_proc_init)
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mov pc, lr
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/*
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* cpu_feroceon_proc_fin()
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*/
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ENTRY(cpu_feroceon_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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bl feroceon_flush_kern_cache_all
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_feroceon_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_feroceon_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_feroceon_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 10
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ENTRY(cpu_feroceon_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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ENTRY(feroceon_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(feroceon_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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#else
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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#endif
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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ENTRY(feroceon_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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#else
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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#endif
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(feroceon_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(feroceon_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
|
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* the I cache
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*
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* - addr - page aligned address
|
||||
*/
|
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ENTRY(feroceon_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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||||
blo 1b
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||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
|
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* dma_inv_range(start, end)
|
||||
*
|
||||
* Invalidate (discard) the specified virtual address range.
|
||||
* May not write back any entries. If 'start' or 'end'
|
||||
* are not cache line aligned, those lines must be written
|
||||
* back.
|
||||
*
|
||||
* - start - virtual start address
|
||||
* - end - virtual end address
|
||||
*
|
||||
* (same as v4wb)
|
||||
*/
|
||||
ENTRY(feroceon_dma_inv_range)
|
||||
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
tst r0, #CACHE_DLINESIZE - 1
|
||||
mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
tst r1, #CACHE_DLINESIZE - 1
|
||||
mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
|
||||
#endif
|
||||
bic r0, r0, #CACHE_DLINESIZE - 1
|
||||
1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
|
||||
add r0, r0, #CACHE_DLINESIZE
|
||||
cmp r0, r1
|
||||
blo 1b
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* dma_clean_range(start, end)
|
||||
*
|
||||
* Clean the specified virtual address range.
|
||||
*
|
||||
* - start - virtual start address
|
||||
* - end - virtual end address
|
||||
*
|
||||
* (same as v4wb)
|
||||
*/
|
||||
ENTRY(feroceon_dma_clean_range)
|
||||
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
bic r0, r0, #CACHE_DLINESIZE - 1
|
||||
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
add r0, r0, #CACHE_DLINESIZE
|
||||
cmp r0, r1
|
||||
blo 1b
|
||||
#endif
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* dma_flush_range(start, end)
|
||||
*
|
||||
* Clean and invalidate the specified virtual address range.
|
||||
*
|
||||
* - start - virtual start address
|
||||
* - end - virtual end address
|
||||
*/
|
||||
ENTRY(feroceon_dma_flush_range)
|
||||
bic r0, r0, #CACHE_DLINESIZE - 1
|
||||
1:
|
||||
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
|
||||
#else
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
#endif
|
||||
add r0, r0, #CACHE_DLINESIZE
|
||||
cmp r0, r1
|
||||
blo 1b
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(feroceon_cache_fns)
|
||||
.long feroceon_flush_kern_cache_all
|
||||
.long feroceon_flush_user_cache_all
|
||||
.long feroceon_flush_user_cache_range
|
||||
.long feroceon_coherent_kern_range
|
||||
.long feroceon_coherent_user_range
|
||||
.long feroceon_flush_kern_dcache_page
|
||||
.long feroceon_dma_inv_range
|
||||
.long feroceon_dma_clean_range
|
||||
.long feroceon_dma_flush_range
|
||||
|
||||
ENTRY(cpu_feroceon_dcache_clean_area)
|
||||
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
add r0, r0, #CACHE_DLINESIZE
|
||||
subs r1, r1, #CACHE_DLINESIZE
|
||||
bhi 1b
|
||||
#endif
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
mov pc, lr
|
||||
|
||||
/* =============================== PageTable ============================== */
|
||||
|
||||
/*
|
||||
* cpu_feroceon_switch_mm(pgd)
|
||||
*
|
||||
* Set the translation base pointer to be as described by pgd.
|
||||
*
|
||||
* pgd: new page tables
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_feroceon_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
mov ip, #0
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
|
||||
#else
|
||||
@ && 'Clean & Invalidate whole DCache'
|
||||
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
|
||||
bne 1b
|
||||
#endif
|
||||
mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* cpu_feroceon_set_pte_ext(ptep, pte, ext)
|
||||
*
|
||||
* Set a PTE and flush it out
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_feroceon_set_pte_ext)
|
||||
#ifdef CONFIG_MMU
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
||||
|
||||
bic r2, r1, #PTE_SMALL_AP_MASK
|
||||
bic r2, r2, #PTE_TYPE_MASK
|
||||
orr r2, r2, #PTE_TYPE_SMALL
|
||||
|
||||
tst r1, #L_PTE_USER @ User?
|
||||
orrne r2, r2, #PTE_SMALL_AP_URO_SRW
|
||||
|
||||
tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
|
||||
orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
|
||||
|
||||
tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
|
||||
movne r2, #0
|
||||
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
eor r3, r2, #0x0a @ C & small page?
|
||||
tst r3, #0x0b
|
||||
biceq r2, r2, #4
|
||||
#endif
|
||||
str r2, [r0] @ hardware version
|
||||
mov r0, r0
|
||||
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
#endif
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
__INIT
|
||||
|
||||
.type __feroceon_setup, #function
|
||||
__feroceon_setup:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mov r0, #4 @ disable write-back on caches explicitly
|
||||
mcr p15, 7, r0, c15, c0, 0
|
||||
#endif
|
||||
|
||||
adr r5, feroceon_crval
|
||||
ldmia r5, {r5, r6}
|
||||
mrc p15, 0, r0, c1, c0 @ get control register v4
|
||||
bic r0, r0, r5
|
||||
orr r0, r0, r6
|
||||
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
||||
orr r0, r0, #0x4000 @ .1.. .... .... ....
|
||||
#endif
|
||||
mov pc, lr
|
||||
.size __feroceon_setup, . - __feroceon_setup
|
||||
|
||||
/*
|
||||
* R
|
||||
* .RVI ZFRS BLDP WCAM
|
||||
* .011 0001 ..11 0101
|
||||
*
|
||||
*/
|
||||
.type feroceon_crval, #object
|
||||
feroceon_crval:
|
||||
crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
|
||||
|
||||
__INITDATA
|
||||
|
||||
/*
|
||||
* Purpose : Function pointers used to access above functions - all calls
|
||||
* come through these
|
||||
*/
|
||||
.type feroceon_processor_functions, #object
|
||||
feroceon_processor_functions:
|
||||
.word v5t_early_abort
|
||||
.word cpu_feroceon_proc_init
|
||||
.word cpu_feroceon_proc_fin
|
||||
.word cpu_feroceon_reset
|
||||
.word cpu_feroceon_do_idle
|
||||
.word cpu_feroceon_dcache_clean_area
|
||||
.word cpu_feroceon_switch_mm
|
||||
.word cpu_feroceon_set_pte_ext
|
||||
.size feroceon_processor_functions, . - feroceon_processor_functions
|
||||
|
||||
.section ".rodata"
|
||||
|
||||
.type cpu_arch_name, #object
|
||||
cpu_arch_name:
|
||||
.asciz "armv5te"
|
||||
.size cpu_arch_name, . - cpu_arch_name
|
||||
|
||||
.type cpu_elf_name, #object
|
||||
cpu_elf_name:
|
||||
.asciz "v5"
|
||||
.size cpu_elf_name, . - cpu_elf_name
|
||||
|
||||
.type cpu_feroceon_name, #object
|
||||
cpu_feroceon_name:
|
||||
.asciz "Feroceon"
|
||||
.size cpu_feroceon_name, . - cpu_feroceon_name
|
||||
|
||||
.align
|
||||
|
||||
.section ".proc.info.init", #alloc, #execinstr
|
||||
|
||||
#ifdef CONFIG_CPU_FEROCEON_OLD_ID
|
||||
.type __feroceon_old_id_proc_info,#object
|
||||
__feroceon_old_id_proc_info:
|
||||
.long 0x41069260
|
||||
.long 0xfffffff0
|
||||
.long PMD_TYPE_SECT | \
|
||||
PMD_SECT_BUFFERABLE | \
|
||||
PMD_SECT_CACHEABLE | \
|
||||
PMD_BIT4 | \
|
||||
PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ
|
||||
.long PMD_TYPE_SECT | \
|
||||
PMD_BIT4 | \
|
||||
PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ
|
||||
b __feroceon_setup
|
||||
.long cpu_arch_name
|
||||
.long cpu_elf_name
|
||||
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
||||
.long cpu_feroceon_name
|
||||
.long feroceon_processor_functions
|
||||
.long v4wbi_tlb_fns
|
||||
.long v4wb_user_fns
|
||||
.long feroceon_cache_fns
|
||||
.size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
|
||||
#endif
|
||||
|
||||
.type __feroceon_proc_info,#object
|
||||
__feroceon_proc_info:
|
||||
.long 0x56055310
|
||||
.long 0xfffffff0
|
||||
.long PMD_TYPE_SECT | \
|
||||
PMD_SECT_BUFFERABLE | \
|
||||
PMD_SECT_CACHEABLE | \
|
||||
PMD_BIT4 | \
|
||||
PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ
|
||||
.long PMD_TYPE_SECT | \
|
||||
PMD_BIT4 | \
|
||||
PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ
|
||||
b __feroceon_setup
|
||||
.long cpu_arch_name
|
||||
.long cpu_elf_name
|
||||
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
||||
.long cpu_feroceon_name
|
||||
.long feroceon_processor_functions
|
||||
.long v4wbi_tlb_fns
|
||||
.long v4wb_user_fns
|
||||
.long feroceon_cache_fns
|
||||
.size __feroceon_proc_info, . - __feroceon_proc_info
|
||||
Reference in New Issue
Block a user