[MIPS] Support for several more SNI RM models.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thomas Bogendoerfer
committed by
Ralf Baechle
Ralf Baechle
parent
5759906ca9
commit
c066a32a89
@@ -5,6 +5,7 @@
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*
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* Copyright (C) 1992 Linus Torvalds
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* Copyright (C) 1994 - 2000 Ralf Baechle
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* Copyright (C) 2006 Thomas Bogendoerfer
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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@@ -15,153 +16,35 @@
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#include <asm/i8259.h>
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#include <asm/io.h>
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#include <asm/sni.h>
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#include <asm/irq.h>
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#include <asm/irq_cpu.h>
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static void enable_pciasic_irq(unsigned int irq)
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{
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unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
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*(volatile u8 *) PCIMT_IRQSEL |= mask;
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}
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void disable_pciasic_irq(unsigned int irq)
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{
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unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
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*(volatile u8 *) PCIMT_IRQSEL &= mask;
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}
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static void end_pciasic_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_pciasic_irq(irq);
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}
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static struct irq_chip pciasic_irq_type = {
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.name = "ASIC-PCI",
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.ack = disable_pciasic_irq,
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.mask = disable_pciasic_irq,
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.mask_ack = disable_pciasic_irq,
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.unmask = enable_pciasic_irq,
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.end = end_pciasic_irq,
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};
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/*
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* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
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* button interrupts. Later ...
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*/
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static void pciasic_hwint0(void)
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{
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panic("Received int0 but no handler yet ...");
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}
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/* This interrupt was used for the com1 console on the first prototypes. */
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static void pciasic_hwint2(void)
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{
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/* I think this shouldn't happen on production machines. */
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panic("hwint2 and no handler yet");
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}
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/* hwint5 is the r4k count / compare interrupt */
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static void pciasic_hwint5(void)
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{
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panic("hwint5 and no handler yet");
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}
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static unsigned int ls1bit8(unsigned int x)
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{
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int b = 7, s;
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s = 4; if ((x & 0x0f) == 0) s = 0; b -= s; x <<= s;
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s = 2; if ((x & 0x30) == 0) s = 0; b -= s; x <<= s;
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s = 1; if ((x & 0x40) == 0) s = 0; b -= s;
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return b;
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}
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/*
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* hwint 1 deals with EISA and SCSI interrupts,
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*
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* The EISA_INT bit in CSITPEND is high active, all others are low active.
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*/
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static void pciasic_hwint1(void)
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{
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u8 pend = *(volatile char *)PCIMT_CSITPEND;
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unsigned long flags;
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if (pend & IT_EISA) {
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int irq;
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/*
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* Note: ASIC PCI's builtin interrupt achknowledge feature is
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* broken. Using it may result in loss of some or all i8259
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* interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
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*/
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irq = i8259_irq();
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if (unlikely(irq < 0))
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return;
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do_IRQ(irq);
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}
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if (!(pend & IT_SCSI)) {
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flags = read_c0_status();
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clear_c0_status(ST0_IM);
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do_IRQ(PCIMT_IRQ_SCSI);
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write_c0_status(flags);
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}
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}
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/*
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* hwint 3 should deal with the PCI A - D interrupts,
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*/
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static void pciasic_hwint3(void)
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{
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u8 pend = *(volatile char *)PCIMT_CSITPEND;
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int irq;
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pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
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clear_c0_status(IE_IRQ3);
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irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
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do_IRQ(irq);
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set_c0_status(IE_IRQ3);
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}
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/*
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* hwint 4 is used for only the onboard PCnet 32.
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*/
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static void pciasic_hwint4(void)
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{
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clear_c0_status(IE_IRQ4);
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do_IRQ(PCIMT_IRQ_ETHERNET);
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set_c0_status(IE_IRQ4);
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}
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void (*sni_hwint)(void);
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause();
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static unsigned char led_cache;
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*(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
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if (pending & 0x0800)
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pciasic_hwint1();
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else if (pending & 0x4000)
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pciasic_hwint4();
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else if (pending & 0x2000)
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pciasic_hwint3();
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else if (pending & 0x1000)
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pciasic_hwint2();
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else if (pending & 0x8000)
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pciasic_hwint5();
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else if (pending & 0x0400)
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pciasic_hwint0();
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sni_hwint();
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}
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void __init init_pciasic(void)
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/* ISA irq handler */
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static irqreturn_t sni_isa_irq_handler(int dummy, void *p)
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{
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* (volatile u8 *) PCIMT_IRQSEL =
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IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
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int irq;
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irq = i8259_irq();
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if (unlikely(irq < 0))
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return IRQ_NONE;
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do_IRQ(irq);
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return IRQ_HANDLED;
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}
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struct irqaction sni_isa_irq = {
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.handler = sni_isa_irq_handler,
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.name = "ISA",
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.flags = SA_SHIRQ
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};
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/*
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* On systems with i8259-style interrupt controllers we assume for
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* driver compatibility reasons interrupts 0 - 15 to be the i8295
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@@ -169,14 +52,31 @@ void __init init_pciasic(void)
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*/
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void __init arch_init_irq(void)
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{
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int i;
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init_i8259_irqs(); /* Integrated i8259 */
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init_pciasic();
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switch (sni_brd_type) {
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case SNI_BRD_10:
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case SNI_BRD_10NEW:
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case SNI_BRD_TOWER_OASIC:
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case SNI_BRD_MINITOWER:
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sni_a20r_irq_init();
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break;
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/* Actually we've got more interrupts to handle ... */
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for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++)
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set_irq_chip(i, &pciasic_irq_type);
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case SNI_BRD_PCI_TOWER:
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sni_pcit_irq_init();
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break;
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change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
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case SNI_BRD_PCI_TOWER_CPLUS:
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sni_pcit_cplus_irq_init();
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break;
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case SNI_BRD_RM200:
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sni_rm200_irq_init();
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break;
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case SNI_BRD_PCI_MTOWER:
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case SNI_BRD_PCI_DESKTOP:
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case SNI_BRD_PCI_MTOWER_CPLUS:
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sni_pcimt_irq_init();
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break;
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}
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}
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