[MIPS] Support for several more SNI RM models.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thomas Bogendoerfer
committed by
Ralf Baechle
Ralf Baechle
parent
5759906ca9
commit
c066a32a89
@ -6,16 +6,10 @@
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* for more details.
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*
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* Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
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*/
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#include <linux/eisa.h>
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#include <linux/hdreg.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/mc146818rtc.h>
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#include <linux/pm.h>
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#include <linux/pci.h>
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#include <linux/console.h>
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#include <linux/fb.h>
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#include <linux/screen_info.h>
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@ -25,52 +19,16 @@
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#include <asm/sgialib.h>
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#endif
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mc146818-time.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/sni.h>
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#include <asm/time.h>
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#include <asm/traps.h>
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unsigned int sni_brd_type;
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extern void sni_machine_restart(char *command);
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extern void sni_machine_halt(void);
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extern void sni_machine_power_off(void);
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void __init plat_timer_setup(struct irqaction *irq)
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{
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/* set the clock to 100 Hz */
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outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
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outb_p(LATCH & 0xff , 0x40); /* LSB */
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outb(LATCH >> 8 , 0x40); /* MSB */
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setup_irq(0, irq);
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}
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/*
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* A bit more gossip about the iron we're running on ...
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*/
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static inline void sni_pcimt_detect(void)
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{
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char boardtype[80];
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unsigned char csmsr;
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char *p = boardtype;
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unsigned int asic;
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csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
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p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
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if ((csmsr & 0x80) == 0)
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p += sprintf(p, ", board revision %s",
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(csmsr & 0x20) ? "D" : "C");
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asic = csmsr & 0x80;
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asic = (csmsr & 0x08) ? asic : !asic;
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p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
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printk("%s.\n", boardtype);
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}
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static void __init sni_display_setup(void)
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{
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#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_ARC)
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@ -90,175 +48,11 @@ static void __init sni_display_setup(void)
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#endif
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}
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static struct resource sni_io_resource = {
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.start = 0x00001000UL,
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.end = 0x03bfffffUL,
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.name = "PCIMT IO MEM",
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.flags = IORESOURCE_IO,
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};
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static struct resource pcimt_io_resources[] = {
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{
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.start = 0x00,
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.end = 0x1f,
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.name = "dma1",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x40,
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.end = 0x5f,
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.name = "timer",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x60,
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.end = 0x6f,
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.name = "keyboard",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x80,
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.end = 0x8f,
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.name = "dma page reg",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0xc0,
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.end = 0xdf,
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.name = "dma2",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0xcfc,
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.end = 0xcff,
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.name = "PCI config data",
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.flags = IORESOURCE_BUSY
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}
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};
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static struct resource sni_mem_resource = {
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.start = 0x10000000UL,
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.end = 0xffffffffUL,
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.name = "PCIMT PCI MEM",
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.flags = IORESOURCE_MEM
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};
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/*
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* The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
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* for other purposes. Be paranoid and allocate all of the before the PCI
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* code gets a chance to to map anything else there ...
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*
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* This leaves the following areas available:
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*
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* 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
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* 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
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* 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
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* 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
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* 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
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*/
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static struct resource pcimt_mem_resources[] = {
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{
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.start = 0x100a0000,
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.end = 0x100bffff,
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.name = "Video RAM area",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x100c0000,
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.end = 0x100fffff,
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.name = "ISA Reserved",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x14000000,
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.end = 0x17bfffff,
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.name = "PCI IO",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x17c00000,
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.end = 0x17ffffff,
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.name = "Cache Replacement Area",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x1a000000,
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.end = 0x1a000003,
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.name = "PCI INT Acknowledge",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x1fc00000,
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.end = 0x1fc7ffff,
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.name = "Boot PROM",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x1fc80000,
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.end = 0x1fcfffff,
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.name = "Diag PROM",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x1fd00000,
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.end = 0x1fdfffff,
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.name = "X-Bus",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x1fe00000,
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.end = 0x1fefffff,
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.name = "BIOS map",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x1ff00000,
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.end = 0x1ff7ffff,
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.name = "NVRAM / EEPROM",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x1fff0000,
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.end = 0x1fffefff,
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.name = "ASIC PCI",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x1ffff000,
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.end = 0x1fffffff,
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.name = "MP Agent",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x20000000,
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.end = 0x9fffffff,
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.name = "Main Memory",
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.flags = IORESOURCE_BUSY
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}
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};
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static void __init sni_resource_init(void)
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{
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int i;
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/* request I/O space for devices used on all i[345]86 PCs */
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for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
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request_resource(&ioport_resource, pcimt_io_resources + i);
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/* request mem space for pcimt-specific devices */
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for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)
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request_resource(&sni_mem_resource, pcimt_mem_resources + i);
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ioport_resource.end = sni_io_resource.end;
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}
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extern struct pci_ops sni_pci_ops;
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static struct pci_controller sni_controller = {
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.pci_ops = &sni_pci_ops,
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.mem_resource = &sni_mem_resource,
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.mem_offset = 0x10000000UL,
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.io_resource = &sni_io_resource,
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.io_offset = 0x00000000UL
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};
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static inline void sni_pcimt_time_init(void)
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{
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rtc_mips_get_time = mc146818_get_cmos_time;
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rtc_mips_set_time = mc146818_set_rtc_mmss;
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}
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void __init plat_mem_setup(void)
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{
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sni_pcimt_detect();
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sni_pcimt_sc_init();
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sni_pcimt_time_init();
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set_io_port_base(SNI_PORT_BASE);
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ioport_resource.end = sni_io_resource.end;
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// ioport_resource.end = sni_io_resource.end;
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/*
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* Setup (E)ISA I/O memory access stuff
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@ -268,15 +62,33 @@ void __init plat_mem_setup(void)
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EISA_bus = 1;
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#endif
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sni_resource_init();
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switch (sni_brd_type) {
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case SNI_BRD_10:
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case SNI_BRD_10NEW:
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case SNI_BRD_TOWER_OASIC:
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case SNI_BRD_MINITOWER:
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sni_a20r_init();
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break;
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case SNI_BRD_PCI_TOWER:
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case SNI_BRD_PCI_TOWER_CPLUS:
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sni_pcit_init();
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break;
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case SNI_BRD_RM200:
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sni_rm200_init();
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break;
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case SNI_BRD_PCI_MTOWER:
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case SNI_BRD_PCI_DESKTOP:
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case SNI_BRD_PCI_MTOWER_CPLUS:
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sni_pcimt_init();
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break;
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}
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_machine_restart = sni_machine_restart;
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_machine_halt = sni_machine_halt;
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pm_power_off = sni_machine_power_off;
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sni_display_setup();
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#ifdef CONFIG_PCI
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register_pci_controller(&sni_controller);
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#endif
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}
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