intel-iommu: Tidy up iommu->gcmd handling
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
@@ -819,7 +819,7 @@ static int iommu_alloc_root_entry(struct intel_iommu *iommu)
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static void iommu_set_root_entry(struct intel_iommu *iommu)
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{
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void *addr;
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u32 cmd, sts;
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u32 sts;
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unsigned long flag;
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addr = iommu->root_entry;
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@@ -827,12 +827,11 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
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spin_lock_irqsave(&iommu->register_lock, flag);
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dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
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cmd = iommu->gcmd | DMA_GCMD_SRTP;
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writel(cmd, iommu->reg + DMAR_GCMD_REG);
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writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_RTPS), sts);
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readl, (sts & DMA_GSTS_RTPS), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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@@ -844,12 +843,13 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)
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if (!rwbf_quirk && !cap_rwbf(iommu->cap))
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return;
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (!(val & DMA_GSTS_WBFS)), val);
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readl, (!(val & DMA_GSTS_WBFS)), val);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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@@ -995,13 +995,13 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
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unsigned long flags;
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spin_lock_irqsave(&iommu->register_lock, flags);
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writel(iommu->gcmd|DMA_GCMD_TE, iommu->reg + DMAR_GCMD_REG);
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iommu->gcmd |= DMA_GCMD_TE;
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_TES), sts);
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readl, (sts & DMA_GSTS_TES), sts);
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iommu->gcmd |= DMA_GCMD_TE;
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spin_unlock_irqrestore(&iommu->register_lock, flags);
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return 0;
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}
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@@ -1017,7 +1017,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
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/* Make sure hardware complete it */
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (!(sts & DMA_GSTS_TES)), sts);
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readl, (!(sts & DMA_GSTS_TES)), sts);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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return 0;
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