ath9k_hw: Enable TX IQ calibration on AR9003
To enable it we now disable and re-enable the PHY chips after TX IQ calibration. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville
parent
252aa631f8
commit
c5395b6743
@@ -739,6 +739,12 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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*/
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*/
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ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
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ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
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/* Do Tx IQ Calibration */
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ar9003_hw_tx_iq_cal(ah);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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udelay(5);
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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/* Calibrate the AGC */
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/* Calibrate the AGC */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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REG_READ(ah, AR_PHY_AGC_CONTROL) |
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@@ -753,10 +759,6 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
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return false;
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return false;
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}
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}
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/* Do Tx IQ Calibration */
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if (ah->config.tx_iq_calibration)
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ar9003_hw_tx_iq_cal(ah);
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/* Revert chainmasks to their original values before NF cal */
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/* Revert chainmasks to their original values before NF cal */
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ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
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ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
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@@ -391,12 +391,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
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ah->config.rx_intr_mitigation = true;
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ah->config.rx_intr_mitigation = true;
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/*
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* Tx IQ Calibration (ah->config.tx_iq_calibration) is only
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* used by AR9003, but it is showing reliability issues.
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* It will take a while to fix so this is currently disabled.
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*/
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/*
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/*
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* We need this for PCI devices only (Cardbus, PCI, miniPCI)
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* We need this for PCI devices only (Cardbus, PCI, miniPCI)
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* _and_ if on non-uniprocessor systems (Multiprocessor/HT).
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* _and_ if on non-uniprocessor systems (Multiprocessor/HT).
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@@ -263,7 +263,6 @@ struct ath9k_ops_config {
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#define AR_BASE_FREQ_5GHZ 4900
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#define AR_BASE_FREQ_5GHZ 4900
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#define AR_SPUR_FEEQ_BOUND_HT40 19
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#define AR_SPUR_FEEQ_BOUND_HT40 19
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#define AR_SPUR_FEEQ_BOUND_HT20 10
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#define AR_SPUR_FEEQ_BOUND_HT20 10
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bool tx_iq_calibration; /* Only available for >= AR9003 */
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int spurmode;
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int spurmode;
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u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
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u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
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u8 max_txtrig_level;
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u8 max_txtrig_level;
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