lk/linux-kernel-test
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

sh: pci: Set pci_cache_line_size on SH7780 via the PCICLS register.

Browse Source 
The SH7780 PCIC contains a read-only cache line size register that we can
derive pci_cache_line_size from. So, make sure that the software idea of
the cache line size actually matches the host controller's idea.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
2009-04-17 16:38:00 +09:00
parent ab78cbcf68
commit c66c1d79a9
1 changed files with 12 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
arch/sh/drivers/pci/pci-sh7780.c
View File

@@ -22,15 +22,6 @@
#include <linux/delay.h> #include <linux/delay.h>
#include "pci-sh4.h" #include "pci-sh4.h"
/*
* Initialization. Try all known PCI access methods. Note that we support
* using both PCI BIOS and direct access: in such cases, we use I/O ports
* to access config space.
*
* Note that the platform specific initialization (BSC registers, and memory
* space mapping) will be called via the platform defined function
* pcibios_init_platform().
*/
int __init sh7780_pci_init(struct pci_channel *chan) int __init sh7780_pci_init(struct pci_channel *chan)
{ {
unsigned int id; unsigned int id;
@@ -70,19 +61,31 @@ int __init sh7780_pci_init(struct pci_channel *chan)
if ((ret = sh4_pci_check_direct(chan)) != 0) if ((ret = sh4_pci_check_direct(chan)) != 0)
return ret; return ret;
/*
* Platform specific initialization (BSC registers, and memory space
* mapping) will be called via the platform defined function
* pcibios_init_platform().
*/
return pcibios_init_platform(); return pcibios_init_platform();
} }
extern u8 pci_cache_line_size;
int __init sh7780_pcic_init(struct pci_channel *chan, int __init sh7780_pcic_init(struct pci_channel *chan,
struct sh4_pci_address_map *map) struct sh4_pci_address_map *map)
{ {
u32 word; u32 word;
/*
* Set the class and sub-class codes.
*/
__raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8, __raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8,
chan->reg_base + SH7780_PCIBCC); chan->reg_base + SH7780_PCIBCC);
__raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff, __raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff,
chan->reg_base + SH7780_PCISUB); chan->reg_base + SH7780_PCISUB);
pci_cache_line_size = pci_read_reg(chan, SH7780_PCICLS) / 4;
/* set the command/status bits to: /* set the command/status bits to:
* Wait Cycle Control + Parity Enable + Bus Master + * Wait Cycle Control + Parity Enable + Bus Master +
* Mem space enable * Mem space enable