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ath9k_hw: Initialize mode registers for AR9485

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Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Vasanthakumar Thiagarajan
2010-12-06 04:27:37 -08:00
committed by John W. Linville
parent 3050c9146b
commit c88457eb83
1 changed files with 119 additions and 56 deletions
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175
drivers/net/wireless/ath/ath9k/ar9003_hw.c
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@@ -17,6 +17,7 @@
#include "hw.h" #include "hw.h"
#include "ar9003_mac.h" #include "ar9003_mac.h"
#include "ar9003_2p2_initvals.h" #include "ar9003_2p2_initvals.h"
#include "ar9485_initvals.h"
/* General hardware code for the AR9003 hadware family */ /* General hardware code for the AR9003 hadware family */
@@ -39,72 +40,134 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
*/ */
static void ar9003_hw_init_mode_regs(struct ath_hw *ah) static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
{ {
/* mac */ if (AR_SREV_9485(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); /* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
ar9300_2p2_mac_core, INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
ARRAY_SIZE(ar9300_2p2_mac_core), 2); ar9485_1_0_mac_core,
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], ARRAY_SIZE(ar9485_1_0_mac_core), 2);
ar9300_2p2_mac_postamble, INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
ARRAY_SIZE(ar9300_2p2_mac_postamble), 5); ar9485_1_0_mac_postamble,
ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
/* bb */ /* bb */
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], ARRAY_SIZE(ar9485_1_0), 2);
ar9300_2p2_baseband_core, INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
ARRAY_SIZE(ar9300_2p2_baseband_core), 2); ar9485_1_0_baseband_core,
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
ar9300_2p2_baseband_postamble, INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5); ar9485_1_0_baseband_postamble,
ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
/* radio */ /* radio */
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
ar9300_2p2_radio_core, ar9485_1_0_radio_core,
ARRAY_SIZE(ar9300_2p2_radio_core), 2); ARRAY_SIZE(ar9485_1_0_radio_core), 2);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
ar9300_2p2_radio_postamble, ar9485_1_0_radio_postamble,
ARRAY_SIZE(ar9300_2p2_radio_postamble), 5); ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
/* soc */ /* soc */
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
ar9300_2p2_soc_preamble, ar9485_1_0_soc_preamble,
ARRAY_SIZE(ar9300_2p2_soc_preamble), 2); ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
ar9300_2p2_soc_postamble,
ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
/* rx/tx gain */ /* rx/tx gain */
INIT_INI_ARRAY(&ah->iniModesRxGain, INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9300Common_rx_gain_table_2p2, ar9485Common_rx_gain_1_0,
ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2); ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9300Modes_lowest_ob_db_tx_gain_table_2p2, ar9485Modes_lowest_ob_db_tx_gain_1_0,
ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
5); 5);
/* Load PCIE SERDES settings from INI */ /* Load PCIE SERDES settings from INI */
/* Awake Setting */ /* Awake Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdes, INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2), ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
2); 2);
/* Sleep Setting */ /* Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9300PciePhy_clkreq_enable_L1_2p2, ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1,
ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2), ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1),
2); 2);
} else {
/* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
ar9300_2p2_mac_core,
ARRAY_SIZE(ar9300_2p2_mac_core), 2);
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
ar9300_2p2_mac_postamble,
ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
/* Fast clock modal settings */ /* bb */
INIT_INI_ARRAY(&ah->iniModesAdditional, INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
ar9300Modes_fast_clock_2p2, INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
ARRAY_SIZE(ar9300Modes_fast_clock_2p2), ar9300_2p2_baseband_core,
3); ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
ar9300_2p2_baseband_postamble,
ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
/* radio */
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
ar9300_2p2_radio_core,
ARRAY_SIZE(ar9300_2p2_radio_core), 2);
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
ar9300_2p2_radio_postamble,
ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
/* soc */
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
ar9300_2p2_soc_preamble,
ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
ar9300_2p2_soc_postamble,
ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
/* rx/tx gain */
INIT_INI_ARRAY(&ah->iniModesRxGain,
ar9300Common_rx_gain_table_2p2,
ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
5);
/* Load PCIE SERDES settings from INI */
/* Awake Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
2);
/* Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9300PciePhy_clkreq_enable_L1_2p2,
ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
2);
/* Fast clock modal settings */
INIT_INI_ARRAY(&ah->iniModesAdditional,
ar9300Modes_fast_clock_2p2,
ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
3);
}
} }
static void ar9003_tx_gain_table_apply(struct ath_hw *ah) static void ar9003_tx_gain_table_apply(struct ath_hw *ah)