sh: Support denormalization on SH-4 FPU.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Stuart Menefy
committed by
Paul Mundt
Paul Mundt
parent
453ec9c1c3
commit
c8c0a1aba9
@ -1,7 +1,4 @@
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/* $Id: fpu.c,v 1.4 2004/01/13 05:52:11 kkojima Exp $
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*
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* linux/arch/sh/kernel/fpu.c
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*
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/*
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* Save/restore floating point context for signal handlers.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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@ -9,15 +6,16 @@
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* for more details.
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*
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* Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
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* Copyright (C) 2006 ST Microelectronics Ltd. (denorm support)
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*
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* FIXME! These routines can be optimized in big endian case.
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* FIXME! These routines have not been tested for big endian case.
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*/
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/io.h>
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#include <asm/cpu/fpu.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/io.h>
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/* The PR (precision) bit in the FP Status Register must be clear when
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* an frchg instruction is executed, otherwise the instruction is undefined.
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@ -25,113 +23,122 @@
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*/
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#define FPSCR_RCHG 0x00000000
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extern unsigned long long float64_div(unsigned long long a,
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unsigned long long b);
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extern unsigned long int float32_div(unsigned long int a, unsigned long int b);
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extern unsigned long long float64_mul(unsigned long long a,
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unsigned long long b);
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extern unsigned long int float32_mul(unsigned long int a, unsigned long int b);
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extern unsigned long long float64_add(unsigned long long a,
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unsigned long long b);
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extern unsigned long int float32_add(unsigned long int a, unsigned long int b);
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extern unsigned long long float64_sub(unsigned long long a,
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unsigned long long b);
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extern unsigned long int float32_sub(unsigned long int a, unsigned long int b);
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static unsigned int fpu_exception_flags;
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/*
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* Save FPU registers onto task structure.
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* Assume called with FPU enabled (SR.FD=0).
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*/
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void
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save_fpu(struct task_struct *tsk, struct pt_regs *regs)
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void save_fpu(struct task_struct *tsk, struct pt_regs *regs)
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{
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unsigned long dummy;
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clear_tsk_thread_flag(tsk, TIF_USEDFPU);
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enable_fpu();
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asm volatile("sts.l fpul, @-%0\n\t"
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"sts.l fpscr, @-%0\n\t"
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"lds %2, fpscr\n\t"
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"frchg\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"frchg\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"lds %3, fpscr\n\t"
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: "=r" (dummy)
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: "0" ((char *)(&tsk->thread.fpu.hard.status)),
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"r" (FPSCR_RCHG),
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"r" (FPSCR_INIT)
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: "memory");
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asm volatile ("sts.l fpul, @-%0\n\t"
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"sts.l fpscr, @-%0\n\t"
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"lds %2, fpscr\n\t"
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"frchg\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"frchg\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"lds %3, fpscr\n\t":"=r" (dummy)
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:"0"((char *)(&tsk->thread.fpu.hard.status)),
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"r"(FPSCR_RCHG), "r"(FPSCR_INIT)
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:"memory");
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disable_fpu();
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release_fpu(regs);
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}
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static void
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restore_fpu(struct task_struct *tsk)
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static void restore_fpu(struct task_struct *tsk)
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{
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unsigned long dummy;
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enable_fpu();
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asm volatile("lds %2, fpscr\n\t"
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"fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"frchg\n\t"
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"fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"frchg\n\t"
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"lds.l @%0+, fpscr\n\t"
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"lds.l @%0+, fpul\n\t"
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: "=r" (dummy)
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: "0" (&tsk->thread.fpu), "r" (FPSCR_RCHG)
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: "memory");
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asm volatile ("lds %2, fpscr\n\t"
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"fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"frchg\n\t"
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"fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"frchg\n\t"
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"lds.l @%0+, fpscr\n\t"
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"lds.l @%0+, fpul\n\t"
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:"=r" (dummy)
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:"0"(&tsk->thread.fpu), "r"(FPSCR_RCHG)
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:"memory");
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disable_fpu();
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}
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@ -141,61 +148,59 @@ restore_fpu(struct task_struct *tsk)
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* double precision represents signaling NANS.
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*/
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static void
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fpu_init(void)
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static void fpu_init(void)
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{
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enable_fpu();
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asm volatile("lds %0, fpul\n\t"
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"lds %1, fpscr\n\t"
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"fsts fpul, fr0\n\t"
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"fsts fpul, fr1\n\t"
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"fsts fpul, fr2\n\t"
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"fsts fpul, fr3\n\t"
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"fsts fpul, fr4\n\t"
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"fsts fpul, fr5\n\t"
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"fsts fpul, fr6\n\t"
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"fsts fpul, fr7\n\t"
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"fsts fpul, fr8\n\t"
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"fsts fpul, fr9\n\t"
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"fsts fpul, fr10\n\t"
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"fsts fpul, fr11\n\t"
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"fsts fpul, fr12\n\t"
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"fsts fpul, fr13\n\t"
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"fsts fpul, fr14\n\t"
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"fsts fpul, fr15\n\t"
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"frchg\n\t"
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"fsts fpul, fr0\n\t"
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"fsts fpul, fr1\n\t"
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"fsts fpul, fr2\n\t"
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"fsts fpul, fr3\n\t"
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"fsts fpul, fr4\n\t"
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"fsts fpul, fr5\n\t"
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"fsts fpul, fr6\n\t"
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"fsts fpul, fr7\n\t"
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"fsts fpul, fr8\n\t"
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"fsts fpul, fr9\n\t"
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"fsts fpul, fr10\n\t"
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"fsts fpul, fr11\n\t"
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"fsts fpul, fr12\n\t"
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"fsts fpul, fr13\n\t"
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"fsts fpul, fr14\n\t"
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"fsts fpul, fr15\n\t"
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"frchg\n\t"
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"lds %2, fpscr\n\t"
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: /* no output */
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: "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
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asm volatile ( "lds %0, fpul\n\t"
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"lds %1, fpscr\n\t"
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"fsts fpul, fr0\n\t"
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"fsts fpul, fr1\n\t"
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"fsts fpul, fr2\n\t"
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"fsts fpul, fr3\n\t"
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"fsts fpul, fr4\n\t"
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"fsts fpul, fr5\n\t"
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"fsts fpul, fr6\n\t"
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"fsts fpul, fr7\n\t"
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"fsts fpul, fr8\n\t"
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"fsts fpul, fr9\n\t"
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"fsts fpul, fr10\n\t"
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"fsts fpul, fr11\n\t"
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"fsts fpul, fr12\n\t"
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"fsts fpul, fr13\n\t"
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"fsts fpul, fr14\n\t"
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"fsts fpul, fr15\n\t"
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"frchg\n\t"
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"fsts fpul, fr0\n\t"
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"fsts fpul, fr1\n\t"
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"fsts fpul, fr2\n\t"
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"fsts fpul, fr3\n\t"
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"fsts fpul, fr4\n\t"
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"fsts fpul, fr5\n\t"
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"fsts fpul, fr6\n\t"
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"fsts fpul, fr7\n\t"
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"fsts fpul, fr8\n\t"
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"fsts fpul, fr9\n\t"
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"fsts fpul, fr10\n\t"
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"fsts fpul, fr11\n\t"
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"fsts fpul, fr12\n\t"
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"fsts fpul, fr13\n\t"
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"fsts fpul, fr14\n\t"
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"fsts fpul, fr15\n\t"
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"frchg\n\t"
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"lds %2, fpscr\n\t"
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: /* no output */
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:"r" (0), "r"(FPSCR_RCHG), "r"(FPSCR_INIT));
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disable_fpu();
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}
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/**
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* denormal_to_double - Given denormalized float number,
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* store double float
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* denormal_to_double - Given denormalized float number,
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* store double float
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*
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* @fpu: Pointer to sh_fpu_hard structure
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* @n: Index to FP register
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* @fpu: Pointer to sh_fpu_hard structure
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* @n: Index to FP register
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*/
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static void
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denormal_to_double (struct sh_fpu_hard_struct *fpu, int n)
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static void denormal_to_double(struct sh_fpu_hard_struct *fpu, int n)
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{
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unsigned long du, dl;
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unsigned long x = fpu->fpul;
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@ -212,7 +217,7 @@ denormal_to_double (struct sh_fpu_hard_struct *fpu, int n)
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dl = x << 29;
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fpu->fp_regs[n] = du;
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fpu->fp_regs[n+1] = dl;
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fpu->fp_regs[n + 1] = dl;
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}
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}
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@ -223,67 +228,191 @@ denormal_to_double (struct sh_fpu_hard_struct *fpu, int n)
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*
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* Returns 1 when it's handled (should not cause exception).
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*/
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static int
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ieee_fpe_handler (struct pt_regs *regs)
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static int ieee_fpe_handler(struct pt_regs *regs)
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{
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unsigned short insn = *(unsigned short *) regs->pc;
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unsigned short insn = *(unsigned short *)regs->pc;
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unsigned short finsn;
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unsigned long nextpc;
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int nib[4] = {
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(insn >> 12) & 0xf,
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(insn >> 8) & 0xf,
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(insn >> 4) & 0xf,
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insn & 0xf};
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insn & 0xf
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};
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if (nib[0] == 0xb ||
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(nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
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regs->pr = regs->pc + 4;
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if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
|
||||
nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */
|
||||
if (nib[0] == 0xb || (nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb))
|
||||
regs->pr = regs->pc + 4; /* bsr & jsr */
|
||||
|
||||
if (nib[0] == 0xa || nib[0] == 0xb) {
|
||||
/* bra & bsr */
|
||||
nextpc = regs->pc + 4 + ((short)((insn & 0xfff) << 4) >> 3);
|
||||
finsn = *(unsigned short *)(regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xd) {
|
||||
/* bt/s */
|
||||
if (regs->sr & 1)
|
||||
nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
|
||||
nextpc = regs->pc + 4 + ((char)(insn & 0xff) << 1);
|
||||
else
|
||||
nextpc = regs->pc + 4;
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */
|
||||
finsn = *(unsigned short *)(regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xf) {
|
||||
/* bf/s */
|
||||
if (regs->sr & 1)
|
||||
nextpc = regs->pc + 4;
|
||||
else
|
||||
nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
nextpc = regs->pc + 4 + ((char)(insn & 0xff) << 1);
|
||||
finsn = *(unsigned short *)(regs->pc + 2);
|
||||
} else if (nib[0] == 0x4 && nib[3] == 0xb &&
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) {
|
||||
/* jmp & jsr */
|
||||
nextpc = regs->regs[nib[1]];
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
finsn = *(unsigned short *)(regs->pc + 2);
|
||||
} else if (nib[0] == 0x0 && nib[3] == 0x3 &&
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) {
|
||||
/* braf & bsrf */
|
||||
nextpc = regs->pc + 4 + regs->regs[nib[1]];
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (insn == 0x000b) { /* rts */
|
||||
finsn = *(unsigned short *)(regs->pc + 2);
|
||||
} else if (insn == 0x000b) {
|
||||
/* rts */
|
||||
nextpc = regs->pr;
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
finsn = *(unsigned short *)(regs->pc + 2);
|
||||
} else {
|
||||
nextpc = regs->pc + instruction_size(insn);
|
||||
finsn = insn;
|
||||
}
|
||||
|
||||
if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
|
||||
if ((finsn & 0xf1ff) == 0xf0ad) {
|
||||
/* fcnvsd */
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
save_fpu(tsk, regs);
|
||||
if ((tsk->thread.fpu.hard.fpscr & (1 << 17))) {
|
||||
if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR))
|
||||
/* FPU error */
|
||||
denormal_to_double (&tsk->thread.fpu.hard,
|
||||
(finsn >> 8) & 0xf);
|
||||
tsk->thread.fpu.hard.fpscr &=
|
||||
~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
|
||||
grab_fpu(regs);
|
||||
restore_fpu(tsk);
|
||||
set_tsk_thread_flag(tsk, TIF_USEDFPU);
|
||||
denormal_to_double(&tsk->thread.fpu.hard,
|
||||
(finsn >> 8) & 0xf);
|
||||
else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
} else if ((finsn & 0xf00f) == 0xf002) {
|
||||
/* fmul */
|
||||
struct task_struct *tsk = current;
|
||||
int fpscr;
|
||||
int n, m, prec;
|
||||
unsigned int hx, hy;
|
||||
|
||||
n = (finsn >> 8) & 0xf;
|
||||
m = (finsn >> 4) & 0xf;
|
||||
hx = tsk->thread.fpu.hard.fp_regs[n];
|
||||
hy = tsk->thread.fpu.hard.fp_regs[m];
|
||||
fpscr = tsk->thread.fpu.hard.fpscr;
|
||||
prec = fpscr & FPSCR_DBL_PRECISION;
|
||||
|
||||
if ((fpscr & FPSCR_CAUSE_ERROR)
|
||||
&& (prec && ((hx & 0x7fffffff) < 0x00100000
|
||||
|| (hy & 0x7fffffff) < 0x00100000))) {
|
||||
long long llx, lly;
|
||||
|
||||
/* FPU error because of denormal (doubles) */
|
||||
llx = ((long long)hx << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[n + 1];
|
||||
lly = ((long long)hy << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[m + 1];
|
||||
llx = float64_mul(llx, lly);
|
||||
tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
|
||||
tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
|
||||
} else if ((fpscr & FPSCR_CAUSE_ERROR)
|
||||
&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
||||
|| (hy & 0x7fffffff) < 0x00800000))) {
|
||||
/* FPU error because of denormal (floats) */
|
||||
hx = float32_mul(hx, hy);
|
||||
tsk->thread.fpu.hard.fp_regs[n] = hx;
|
||||
} else
|
||||
force_sig(SIGFPE, tsk);
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
} else if ((finsn & 0xf00e) == 0xf000) {
|
||||
/* fadd, fsub */
|
||||
struct task_struct *tsk = current;
|
||||
int fpscr;
|
||||
int n, m, prec;
|
||||
unsigned int hx, hy;
|
||||
|
||||
n = (finsn >> 8) & 0xf;
|
||||
m = (finsn >> 4) & 0xf;
|
||||
hx = tsk->thread.fpu.hard.fp_regs[n];
|
||||
hy = tsk->thread.fpu.hard.fp_regs[m];
|
||||
fpscr = tsk->thread.fpu.hard.fpscr;
|
||||
prec = fpscr & FPSCR_DBL_PRECISION;
|
||||
|
||||
if ((fpscr & FPSCR_CAUSE_ERROR)
|
||||
&& (prec && ((hx & 0x7fffffff) < 0x00100000
|
||||
|| (hy & 0x7fffffff) < 0x00100000))) {
|
||||
long long llx, lly;
|
||||
|
||||
/* FPU error because of denormal (doubles) */
|
||||
llx = ((long long)hx << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[n + 1];
|
||||
lly = ((long long)hy << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[m + 1];
|
||||
if ((finsn & 0xf00f) == 0xf000)
|
||||
llx = float64_add(llx, lly);
|
||||
else
|
||||
llx = float64_sub(llx, lly);
|
||||
tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
|
||||
tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
|
||||
} else if ((fpscr & FPSCR_CAUSE_ERROR)
|
||||
&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
||||
|| (hy & 0x7fffffff) < 0x00800000))) {
|
||||
/* FPU error because of denormal (floats) */
|
||||
if ((finsn & 0xf00f) == 0xf000)
|
||||
hx = float32_add(hx, hy);
|
||||
else
|
||||
hx = float32_sub(hx, hy);
|
||||
tsk->thread.fpu.hard.fp_regs[n] = hx;
|
||||
} else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
} else if ((finsn & 0xf003) == 0xf003) {
|
||||
/* fdiv */
|
||||
struct task_struct *tsk = current;
|
||||
int fpscr;
|
||||
int n, m, prec;
|
||||
unsigned int hx, hy;
|
||||
|
||||
n = (finsn >> 8) & 0xf;
|
||||
m = (finsn >> 4) & 0xf;
|
||||
hx = tsk->thread.fpu.hard.fp_regs[n];
|
||||
hy = tsk->thread.fpu.hard.fp_regs[m];
|
||||
fpscr = tsk->thread.fpu.hard.fpscr;
|
||||
prec = fpscr & FPSCR_DBL_PRECISION;
|
||||
|
||||
if ((fpscr & FPSCR_CAUSE_ERROR)
|
||||
&& (prec && ((hx & 0x7fffffff) < 0x00100000
|
||||
|| (hy & 0x7fffffff) < 0x00100000))) {
|
||||
long long llx, lly;
|
||||
|
||||
/* FPU error because of denormal (doubles) */
|
||||
llx = ((long long)hx << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[n + 1];
|
||||
lly = ((long long)hy << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[m + 1];
|
||||
|
||||
llx = float64_div(llx, lly);
|
||||
|
||||
tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
|
||||
tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
|
||||
} else if ((fpscr & FPSCR_CAUSE_ERROR)
|
||||
&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
||||
|| (hy & 0x7fffffff) < 0x00800000))) {
|
||||
/* FPU error because of denormal (floats) */
|
||||
hx = float32_div(hx, hy);
|
||||
tsk->thread.fpu.hard.fp_regs[n] = hx;
|
||||
} else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
@ -292,16 +421,41 @@ ieee_fpe_handler (struct pt_regs *regs)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void float_raise(unsigned int flags)
|
||||
{
|
||||
fpu_exception_flags |= flags;
|
||||
}
|
||||
|
||||
int float_rounding_mode(void)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.fpu.hard.fpscr);
|
||||
return roundingMode;
|
||||
}
|
||||
|
||||
BUILD_TRAP_HANDLER(fpu_error)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
TRAP_HANDLER_DECL;
|
||||
|
||||
if (ieee_fpe_handler(regs))
|
||||
return;
|
||||
|
||||
regs->pc += 2;
|
||||
save_fpu(tsk, regs);
|
||||
fpu_exception_flags = 0;
|
||||
if (ieee_fpe_handler(regs)) {
|
||||
tsk->thread.fpu.hard.fpscr &=
|
||||
~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
|
||||
tsk->thread.fpu.hard.fpscr |= fpu_exception_flags;
|
||||
/* Set the FPSCR flag as well as cause bits - simply
|
||||
* replicate the cause */
|
||||
tsk->thread.fpu.hard.fpscr |= (fpu_exception_flags >> 10);
|
||||
grab_fpu(regs);
|
||||
restore_fpu(tsk);
|
||||
set_tsk_thread_flag(tsk, TIF_USEDFPU);
|
||||
if ((((tsk->thread.fpu.hard.fpscr & FPSCR_ENABLE_MASK) >> 7) &
|
||||
(fpu_exception_flags >> 2)) == 0) {
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
force_sig(SIGFPE, tsk);
|
||||
}
|
||||
|
||||
@ -319,7 +473,7 @@ BUILD_TRAP_HANDLER(fpu_state_restore)
|
||||
if (used_math()) {
|
||||
/* Using the FPU again. */
|
||||
restore_fpu(tsk);
|
||||
} else {
|
||||
} else {
|
||||
/* First time FPU user. */
|
||||
fpu_init();
|
||||
set_used_math();
|
||||
|
||||
Reference in New Issue
Block a user