[MIPS] remove LASAT Networks platforms support
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yoichi Yuasa
committed by
Ralf Baechle
Ralf Baechle
parent
ecd27b92fb
commit
c99cabf034
@@ -11,7 +11,6 @@ obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
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obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
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obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o
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obj-$(CONFIG_MIPS_MSC) += ops-msc.o
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obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
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obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
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obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
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obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
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@@ -22,7 +21,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
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#
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obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
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obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
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obj-$(CONFIG_LASAT) += pci-lasat.o
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obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
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obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
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obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
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@@ -1,147 +0,0 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/bootinfo.h>
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#include <asm/lasat/lasat.h>
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#include <asm/gt64120.h>
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#include <asm/nile4.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#define LO(reg) (reg / 4)
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#define HI(reg) (reg / 4 + 1)
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volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
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static DEFINE_SPINLOCK(nile4_pci_lock);
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static int nile4_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
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{
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unsigned char busnum = bus->number;
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u32 adr, mask, err;
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if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
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/* The addressing scheme chosen leaves room for just
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* 8 devices on the first busnum (besides the PCI
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* controller itself) */
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return PCIBIOS_DEVICE_NOT_FOUND;
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if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
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/* Access controller registers directly */
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if (access_type == PCI_ACCESS_WRITE) {
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vrc_pciregs[(0x200 + where) >> 2] = *val;
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} else {
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*val = vrc_pciregs[(0x200 + where) >> 2];
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}
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return PCIBIOS_SUCCESSFUL;
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}
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/* Temporarily map PCI Window 1 to config space */
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mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
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vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
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/* Clear PCI Error register. This also clears the Error Type
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* bits in the Control register */
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vrc_pciregs[LO(NILE4_PCIERR)] = 0;
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vrc_pciregs[HI(NILE4_PCIERR)] = 0;
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/* Setup address */
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if (busnum == 0)
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adr =
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KSEG1ADDR(PCI_WINDOW1) +
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((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
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| (where & ~3));
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else
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adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |
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(where & ~3);
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if (access_type == PCI_ACCESS_WRITE)
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*(u32 *) adr = *val;
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else
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*val = *(u32 *) adr;
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/* Check for master or target abort */
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err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
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/* Restore PCI Window 1 */
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vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
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if (err)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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unsigned long flags;
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u32 data = 0;
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int err;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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spin_lock_irqsave(&nile4_pci_lock, flags);
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err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
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&data);
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spin_unlock_irqrestore(&nile4_pci_lock, flags);
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if (err)
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return err;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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unsigned long flags;
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u32 data = 0;
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int err;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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spin_lock_irqsave(&nile4_pci_lock, flags);
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err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
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&data);
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spin_unlock_irqrestore(&nile4_pci_lock, flags);
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if (err)
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return err;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else
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data = val;
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if (nile4_pcibios_config_access
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(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops nile4_pci_ops = {
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.read = nile4_pcibios_read,
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.write = nile4_pcibios_write,
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};
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@@ -1,91 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000, 2001, 04 Keith M Wesolowski
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/bootinfo.h>
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extern struct pci_ops nile4_pci_ops;
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extern struct pci_ops gt64xxx_pci0_ops;
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static struct resource lasat_pci_mem_resource = {
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.name = "LASAT PCI MEM",
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.start = 0x18000000,
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.end = 0x19ffffff,
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.flags = IORESOURCE_MEM,
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};
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static struct resource lasat_pci_io_resource = {
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.name = "LASAT PCI IO",
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.start = 0x1a000000,
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.end = 0x1bffffff,
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.flags = IORESOURCE_IO,
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};
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static struct pci_controller lasat_pci_controller = {
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.mem_resource = &lasat_pci_mem_resource,
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.io_resource = &lasat_pci_io_resource,
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};
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static int __init lasat_pci_setup(void)
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{
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printk("PCI: starting\n");
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switch (mips_machtype) {
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case MACH_LASAT_100:
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lasat_pci_controller.pci_ops = >64xxx_pci0_ops;
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break;
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case MACH_LASAT_200:
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lasat_pci_controller.pci_ops = &nile4_pci_ops;
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break;
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default:
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panic("pcibios_init: mips_machtype incorrect");
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}
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register_pci_controller(&lasat_pci_controller);
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return 0;
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}
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arch_initcall(lasat_pci_setup);
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#define LASATINT_ETH1 0
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#define LASATINT_ETH0 1
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#define LASATINT_HDC 2
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#define LASATINT_COMP 3
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#define LASATINT_HDLC 4
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#define LASATINT_PCIA 5
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#define LASATINT_PCIB 6
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#define LASATINT_PCIC 7
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#define LASATINT_PCID 8
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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switch (slot) {
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case 1:
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case 2:
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case 3:
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return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4);
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case 4:
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return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
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case 5:
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return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
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case 6:
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return LASATINT_HDC; /* IDE controller */
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default:
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return 0xff; /* Illegal */
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}
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return -1;
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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