sh: Preparation for uncached jumps through PMB.
Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Paul Mundt
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325df7f204
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cbaa118ecf
@@ -144,6 +144,8 @@ extern unsigned int instruction_size(unsigned int insn);
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#define instruction_size(insn) (4)
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#endif
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extern unsigned long cached_to_uncached;
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/* XXX
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* disable hlt during certain critical i/o operations
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*/
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