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tg3: Allow DMAs to cross cacheline boundaries

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By default, the 5717 (and future chips) break up PCIe DMA packets across
cacheline boundaries.  This isn't necessary on x86.  This patch
selectively loosens the restriction.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
2009-11-13 13:03:40 +00:00
committed by David S. Miller
parent 615774fe59
commit cbf9ca6cf8
2 changed files with 16 additions and 7 deletions
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3
drivers/net/tg3.h
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@@ -142,8 +142,7 @@
#define METAL_REV_B1 0x01
#define METAL_REV_B2 0x02
#define TG3PCI_DMA_RW_CTRL 0x0000006c
#define DMA_RWCTRL_MIN_DMA 0x000000ff
#define DMA_RWCTRL_MIN_DMA_SHIFT 0
#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
#define DMA_RWCTRL_READ_BNDRY_16 0x00000100