Revert "PCI: PCIE ASPM support"
This reverts commit 6c723d5bd8.
It caused build errors on non-x86 platforms, config file confusion, and
even some boot errors on some x86-64 boxes. All around, not quite ready
for prime-time :(
Cc: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman
@@ -1,802 +0,0 @@
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/*
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* File: drivers/pci/pcie/aspm.c
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* Enabling PCIE link L0s/L1 state and Clock Power Management
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*
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* Copyright (C) 2007 Intel
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* Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
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* Copyright (C) Shaohua Li (shaohua.li@intel.com)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/errno.h>
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#include <linux/pm.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/aspm.h>
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#include <acpi/acpi_bus.h>
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#include <linux/pci-acpi.h>
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#include "../pci.h"
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#ifdef MODULE_PARAM_PREFIX
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#undef MODULE_PARAM_PREFIX
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#endif
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#define MODULE_PARAM_PREFIX "pcie_aspm."
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struct endpoint_state {
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unsigned int l0s_acceptable_latency;
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unsigned int l1_acceptable_latency;
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};
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struct pcie_link_state {
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struct list_head sibiling;
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struct pci_dev *pdev;
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/* ASPM state */
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unsigned int support_state;
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unsigned int enabled_state;
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unsigned int bios_aspm_state;
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/* upstream component */
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unsigned int l0s_upper_latency;
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unsigned int l1_upper_latency;
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/* downstream component */
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unsigned int l0s_down_latency;
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unsigned int l1_down_latency;
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/* Clock PM state*/
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unsigned int clk_pm_capable;
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unsigned int clk_pm_enabled;
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unsigned int bios_clk_state;
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/*
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* A pcie downstream port only has one slot under it, so at most there
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* are 8 functions
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*/
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struct endpoint_state endpoints[8];
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};
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static int aspm_disabled;
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static DEFINE_MUTEX(aspm_lock);
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static LIST_HEAD(link_list);
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#define POLICY_DEFAULT 0 /* BIOS default setting */
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#define POLICY_PERFORMANCE 1 /* high performance */
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#define POLICY_POWERSAVE 2 /* high power saving */
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static int aspm_policy;
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static const char *policy_str[] = {
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[POLICY_DEFAULT] = "default",
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[POLICY_PERFORMANCE] = "performance",
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[POLICY_POWERSAVE] = "powersave"
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};
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static int policy_to_aspm_state(struct pci_dev *pdev)
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{
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struct pcie_link_state *link_state = pdev->link_state;
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switch (aspm_policy) {
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case POLICY_PERFORMANCE:
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/* Disable ASPM and Clock PM */
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return 0;
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case POLICY_POWERSAVE:
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/* Enable ASPM L0s/L1 */
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return PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
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case POLICY_DEFAULT:
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return link_state->bios_aspm_state;
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}
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return 0;
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}
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static int policy_to_clkpm_state(struct pci_dev *pdev)
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{
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struct pcie_link_state *link_state = pdev->link_state;
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switch (aspm_policy) {
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case POLICY_PERFORMANCE:
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/* Disable ASPM and Clock PM */
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return 0;
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case POLICY_POWERSAVE:
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/* Disable Clock PM */
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return 1;
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case POLICY_DEFAULT:
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return link_state->bios_clk_state;
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}
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return 0;
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}
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static void pcie_set_clock_pm(struct pci_dev *pdev, int enable)
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{
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struct pci_dev *child_dev;
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int pos;
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u16 reg16;
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struct pcie_link_state *link_state = pdev->link_state;
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list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
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pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
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if (!pos)
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return;
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pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16);
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if (enable)
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reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
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else
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reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
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pci_write_config_word(child_dev, pos + PCI_EXP_LNKCTL, reg16);
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}
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link_state->clk_pm_enabled = !!enable;
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}
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static void pcie_check_clock_pm(struct pci_dev *pdev)
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{
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int pos;
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u32 reg32;
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u16 reg16;
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int capable = 1, enabled = 1;
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struct pci_dev *child_dev;
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struct pcie_link_state *link_state = pdev->link_state;
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/* All functions should have the same cap and state, take the worst */
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list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
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pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
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if (!pos)
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return;
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pci_read_config_dword(child_dev, pos + PCI_EXP_LNKCAP, ®32);
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if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
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capable = 0;
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enabled = 0;
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break;
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}
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pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16);
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if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
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enabled = 0;
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}
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link_state->clk_pm_capable = capable;
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link_state->clk_pm_enabled = enabled;
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link_state->bios_clk_state = enabled;
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pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
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}
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/*
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* pcie_aspm_configure_common_clock: check if the 2 ends of a link
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* could use common clock. If they are, configure them to use the
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* common clock. That will reduce the ASPM state exit latency.
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*/
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static void pcie_aspm_configure_common_clock(struct pci_dev *pdev)
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{
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int pos, child_pos;
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u16 reg16 = 0;
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struct pci_dev *child_dev;
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int same_clock = 1;
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/*
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* all functions of a slot should have the same Slot Clock
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* Configuration, so just check one function
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* */
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child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
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bus_list);
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BUG_ON(!child_dev->is_pcie);
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/* Check downstream component if bit Slot Clock Configuration is 1 */
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child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
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pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_SLC))
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same_clock = 0;
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/* Check upstream component if bit Slot Clock Configuration is 1 */
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pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_SLC))
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same_clock = 0;
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/* Configure downstream component, all functions */
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list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
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child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
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pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
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®16);
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if (same_clock)
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reg16 |= PCI_EXP_LNKCTL_CCC;
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else
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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pci_write_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
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reg16);
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}
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/* Configure upstream component */
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pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
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if (same_clock)
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reg16 |= PCI_EXP_LNKCTL_CCC;
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else
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
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/* retrain link */
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reg16 |= PCI_EXP_LNKCTL_RL;
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pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
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/* Wait for link training end */
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while (1) {
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pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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cpu_relax();
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}
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}
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/*
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* calc_L0S_latency: Convert L0s latency encoding to ns
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*/
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static unsigned int calc_L0S_latency(unsigned int latency_encoding, int ac)
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{
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unsigned int ns = 64;
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if (latency_encoding == 0x7) {
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if (ac)
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ns = -1U;
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else
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ns = 5*1000; /* > 4us */
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} else
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ns *= (1 << latency_encoding);
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return ns;
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}
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/*
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* calc_L1_latency: Convert L1 latency encoding to ns
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*/
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static unsigned int calc_L1_latency(unsigned int latency_encoding, int ac)
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{
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unsigned int ns = 1000;
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if (latency_encoding == 0x7) {
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if (ac)
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ns = -1U;
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else
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ns = 65*1000; /* > 64us */
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} else
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ns *= (1 << latency_encoding);
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return ns;
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}
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static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state,
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unsigned int *l0s, unsigned int *l1, unsigned int *enabled)
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{
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int pos;
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u16 reg16;
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u32 reg32;
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unsigned int latency;
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pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32);
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*state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
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if (*state != PCIE_LINK_STATE_L0S &&
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*state != (PCIE_LINK_STATE_L1|PCIE_LINK_STATE_L0S))
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* state = 0;
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if (*state == 0)
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return;
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latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
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*l0s = calc_L0S_latency(latency, 0);
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if (*state & PCIE_LINK_STATE_L1) {
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latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
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*l1 = calc_L1_latency(latency, 0);
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}
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pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
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*enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1);
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}
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static void pcie_aspm_cap_init(struct pci_dev *pdev)
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{
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struct pci_dev *child_dev;
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u32 state, tmp;
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struct pcie_link_state *link_state = pdev->link_state;
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/* upstream component states */
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pcie_aspm_get_cap_device(pdev, &link_state->support_state,
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&link_state->l0s_upper_latency,
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&link_state->l1_upper_latency,
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&link_state->enabled_state);
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/* downstream component states, all functions have the same setting */
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child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
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bus_list);
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pcie_aspm_get_cap_device(child_dev, &state,
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&link_state->l0s_down_latency,
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&link_state->l1_down_latency,
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&tmp);
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link_state->support_state &= state;
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if (!link_state->support_state)
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return;
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link_state->enabled_state &= link_state->support_state;
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link_state->bios_aspm_state = link_state->enabled_state;
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/* ENDPOINT states*/
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list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
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int pos;
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u32 reg32;
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unsigned int latency;
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struct endpoint_state *ep_state =
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&link_state->endpoints[PCI_FUNC(child_dev->devfn)];
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if (child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
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child_dev->pcie_type != PCI_EXP_TYPE_LEG_END)
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continue;
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pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
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pci_read_config_dword(child_dev, pos + PCI_EXP_DEVCAP, ®32);
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latency = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
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latency = calc_L0S_latency(latency, 1);
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ep_state->l0s_acceptable_latency = latency;
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if (link_state->support_state & PCIE_LINK_STATE_L1) {
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latency = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
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latency = calc_L1_latency(latency, 1);
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ep_state->l1_acceptable_latency = latency;
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}
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}
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}
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static unsigned int __pcie_aspm_check_state_one(struct pci_dev *pdev,
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unsigned int state)
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{
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struct pci_dev *parent_dev, *tmp_dev;
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unsigned int latency, l1_latency = 0;
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struct pcie_link_state *link_state;
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struct endpoint_state *ep_state;
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parent_dev = pdev->bus->self;
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link_state = parent_dev->link_state;
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state &= link_state->support_state;
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if (state == 0)
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return 0;
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ep_state = &link_state->endpoints[PCI_FUNC(pdev->devfn)];
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/*
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* Check latency for endpoint device.
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* TBD: The latency from the endpoint to root complex vary per
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* switch's upstream link state above the device. Here we just do a
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* simple check which assumes all links above the device can be in L1
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* state, that is we just consider the worst case. If switch's upstream
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* link can't be put into L0S/L1, then our check is too strictly.
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*/
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tmp_dev = pdev;
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while (state & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
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parent_dev = tmp_dev->bus->self;
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link_state = parent_dev->link_state;
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if (state & PCIE_LINK_STATE_L0S) {
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latency = max_t(unsigned int,
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link_state->l0s_upper_latency,
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link_state->l0s_down_latency);
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if (latency > ep_state->l0s_acceptable_latency)
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state &= ~PCIE_LINK_STATE_L0S;
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}
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if (state & PCIE_LINK_STATE_L1) {
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latency = max_t(unsigned int,
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link_state->l1_upper_latency,
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link_state->l1_down_latency);
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if (latency + l1_latency >
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ep_state->l1_acceptable_latency)
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state &= ~PCIE_LINK_STATE_L1;
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}
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if (!parent_dev->bus->self) /* parent_dev is a root port */
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break;
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else {
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/*
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* parent_dev is the downstream port of a switch, make
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* tmp_dev the upstream port of the switch
|
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*/
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tmp_dev = parent_dev->bus->self;
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/*
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* every switch on the path to root complex need 1 more
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* microsecond for L1. Spec doesn't mention L0S.
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*/
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if (state & PCIE_LINK_STATE_L1)
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l1_latency += 1000;
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}
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}
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return state;
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}
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static unsigned int pcie_aspm_check_state(struct pci_dev *pdev,
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unsigned int state)
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{
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struct pci_dev *child_dev;
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/* If no child, disable the link */
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if (list_empty(&pdev->subordinate->devices))
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return 0;
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list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
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if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
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/*
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* If downstream component of a link is pci bridge, we
|
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* disable ASPM for now for the link
|
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* */
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state = 0;
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break;
|
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}
|
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if ((child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
|
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child_dev->pcie_type != PCI_EXP_TYPE_LEG_END))
|
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continue;
|
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/* Device not in D0 doesn't need check latency */
|
||||
if (child_dev->current_state == PCI_D1 ||
|
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child_dev->current_state == PCI_D2 ||
|
||||
child_dev->current_state == PCI_D3hot ||
|
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child_dev->current_state == PCI_D3cold)
|
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continue;
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state = __pcie_aspm_check_state_one(child_dev, state);
|
||||
}
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return state;
|
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}
|
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static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state)
|
||||
{
|
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u16 reg16;
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int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
|
||||
|
||||
pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16);
|
||||
reg16 &= ~0x3;
|
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reg16 |= state;
|
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pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
|
||||
}
|
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|
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static void __pcie_aspm_config_link(struct pci_dev *pdev, unsigned int state)
|
||||
{
|
||||
struct pci_dev *child_dev;
|
||||
int valid = 1;
|
||||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
/*
|
||||
* if the downstream component has pci bridge function, don't do ASPM
|
||||
* now
|
||||
*/
|
||||
list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
|
||||
if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
|
||||
valid = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!valid)
|
||||
return;
|
||||
|
||||
/*
|
||||
* spec 2.0 suggests all functions should be configured the same
|
||||
* setting for ASPM. Enabling ASPM L1 should be done in upstream
|
||||
* component first and then downstream, and vice versa for disabling
|
||||
* ASPM L1. Spec doesn't mention L0S.
|
||||
*/
|
||||
if (state & PCIE_LINK_STATE_L1)
|
||||
__pcie_aspm_config_one_dev(pdev, state);
|
||||
|
||||
list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list)
|
||||
__pcie_aspm_config_one_dev(child_dev, state);
|
||||
|
||||
if (!(state & PCIE_LINK_STATE_L1))
|
||||
__pcie_aspm_config_one_dev(pdev, state);
|
||||
|
||||
link_state->enabled_state = state;
|
||||
}
|
||||
|
||||
static void __pcie_aspm_configure_link_state(struct pci_dev *pdev,
|
||||
unsigned int state)
|
||||
{
|
||||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
if (link_state->support_state == 0)
|
||||
return;
|
||||
state &= PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
|
||||
|
||||
/* state 0 means disabling aspm */
|
||||
state = pcie_aspm_check_state(pdev, state);
|
||||
if (link_state->enabled_state == state)
|
||||
return;
|
||||
__pcie_aspm_config_link(pdev, state);
|
||||
}
|
||||
|
||||
/*
|
||||
* pcie_aspm_configure_link_state: enable/disable PCI express link state
|
||||
* @pdev: the root port or switch downstream port
|
||||
*/
|
||||
static void pcie_aspm_configure_link_state(struct pci_dev *pdev,
|
||||
unsigned int state)
|
||||
{
|
||||
down_read(&pci_bus_sem);
|
||||
mutex_lock(&aspm_lock);
|
||||
__pcie_aspm_configure_link_state(pdev, state);
|
||||
mutex_unlock(&aspm_lock);
|
||||
up_read(&pci_bus_sem);
|
||||
}
|
||||
|
||||
static void free_link_state(struct pci_dev *pdev)
|
||||
{
|
||||
kfree(pdev->link_state);
|
||||
pdev->link_state = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* pcie_aspm_init_link_state: Initiate PCI express link state.
|
||||
* It is called after the pcie and its children devices are scaned.
|
||||
* @pdev: the root port or switch downstream port
|
||||
*/
|
||||
void pcie_aspm_init_link_state(struct pci_dev *pdev)
|
||||
{
|
||||
unsigned int state;
|
||||
struct pcie_link_state *link_state;
|
||||
int error = 0;
|
||||
|
||||
if (aspm_disabled || !pdev->is_pcie || pdev->link_state)
|
||||
return;
|
||||
if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
|
||||
return;
|
||||
down_read(&pci_bus_sem);
|
||||
if (list_empty(&pdev->subordinate->devices))
|
||||
goto out;
|
||||
|
||||
mutex_lock(&aspm_lock);
|
||||
|
||||
link_state = kzalloc(sizeof(*link_state), GFP_KERNEL);
|
||||
if (!link_state)
|
||||
goto unlock_out;
|
||||
pdev->link_state = link_state;
|
||||
|
||||
pcie_aspm_configure_common_clock(pdev);
|
||||
|
||||
pcie_aspm_cap_init(pdev);
|
||||
|
||||
/* config link state to avoid BIOS error */
|
||||
state = pcie_aspm_check_state(pdev, policy_to_aspm_state(pdev));
|
||||
__pcie_aspm_config_link(pdev, state);
|
||||
|
||||
pcie_check_clock_pm(pdev);
|
||||
|
||||
link_state->pdev = pdev;
|
||||
list_add(&link_state->sibiling, &link_list);
|
||||
|
||||
unlock_out:
|
||||
if (error)
|
||||
free_link_state(pdev);
|
||||
mutex_unlock(&aspm_lock);
|
||||
out:
|
||||
up_read(&pci_bus_sem);
|
||||
}
|
||||
|
||||
/* @pdev: the endpoint device */
|
||||
void pcie_aspm_exit_link_state(struct pci_dev *pdev)
|
||||
{
|
||||
struct pci_dev *parent = pdev->bus->self;
|
||||
struct pcie_link_state *link_state = parent->link_state;
|
||||
|
||||
if (aspm_disabled || !pdev->is_pcie || !parent || !link_state)
|
||||
return;
|
||||
if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
|
||||
return;
|
||||
down_read(&pci_bus_sem);
|
||||
mutex_lock(&aspm_lock);
|
||||
|
||||
/*
|
||||
* All PCIe functions are in one slot, remove one function will remove
|
||||
* the the whole slot, so just wait
|
||||
*/
|
||||
if (!list_empty(&parent->subordinate->devices))
|
||||
goto out;
|
||||
|
||||
/* All functions are removed, so just disable ASPM for the link */
|
||||
__pcie_aspm_config_one_dev(parent, 0);
|
||||
list_del(&link_state->sibiling);
|
||||
/* Clock PM is for endpoint device */
|
||||
|
||||
free_link_state(parent);
|
||||
out:
|
||||
mutex_unlock(&aspm_lock);
|
||||
up_read(&pci_bus_sem);
|
||||
}
|
||||
|
||||
/* @pdev: the root port or switch downstream port */
|
||||
void pcie_aspm_pm_state_change(struct pci_dev *pdev)
|
||||
{
|
||||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
if (aspm_disabled || !pdev->is_pcie || !pdev->link_state)
|
||||
return;
|
||||
if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
|
||||
return;
|
||||
/*
|
||||
* devices changed PM state, we should recheck if latency meets all
|
||||
* functions' requirement
|
||||
*/
|
||||
pcie_aspm_configure_link_state(pdev, link_state->enabled_state);
|
||||
}
|
||||
|
||||
/*
|
||||
* pci_disable_link_state - disable pci device's link state, so the link will
|
||||
* never enter specific states
|
||||
*/
|
||||
void pci_disable_link_state(struct pci_dev *pdev, int state)
|
||||
{
|
||||
struct pci_dev *parent = pdev->bus->self;
|
||||
struct pcie_link_state *link_state;
|
||||
|
||||
if (aspm_disabled || !pdev->is_pcie)
|
||||
return;
|
||||
if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
|
||||
pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
|
||||
parent = pdev;
|
||||
if (!parent)
|
||||
return;
|
||||
|
||||
down_read(&pci_bus_sem);
|
||||
mutex_lock(&aspm_lock);
|
||||
link_state = parent->link_state;
|
||||
link_state->support_state &=
|
||||
~(state & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1));
|
||||
if (state & PCIE_LINK_STATE_CLKPM)
|
||||
link_state->clk_pm_capable = 0;
|
||||
|
||||
__pcie_aspm_configure_link_state(parent, link_state->enabled_state);
|
||||
if (!link_state->clk_pm_capable && link_state->clk_pm_enabled)
|
||||
pcie_set_clock_pm(parent, 0);
|
||||
mutex_unlock(&aspm_lock);
|
||||
up_read(&pci_bus_sem);
|
||||
}
|
||||
EXPORT_SYMBOL(pci_disable_link_state);
|
||||
|
||||
static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
|
||||
{
|
||||
int i;
|
||||
struct pci_dev *pdev;
|
||||
struct pcie_link_state *link_state;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(policy_str); i++)
|
||||
if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
|
||||
break;
|
||||
if (i >= ARRAY_SIZE(policy_str))
|
||||
return -EINVAL;
|
||||
if (i == aspm_policy)
|
||||
return 0;
|
||||
|
||||
down_read(&pci_bus_sem);
|
||||
mutex_lock(&aspm_lock);
|
||||
aspm_policy = i;
|
||||
list_for_each_entry(link_state, &link_list, sibiling) {
|
||||
pdev = link_state->pdev;
|
||||
__pcie_aspm_configure_link_state(pdev,
|
||||
policy_to_aspm_state(pdev));
|
||||
if (link_state->clk_pm_capable &&
|
||||
link_state->clk_pm_enabled != policy_to_clkpm_state(pdev))
|
||||
pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
|
||||
|
||||
}
|
||||
mutex_unlock(&aspm_lock);
|
||||
up_read(&pci_bus_sem);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
|
||||
{
|
||||
int i, cnt = 0;
|
||||
for (i = 0; i < ARRAY_SIZE(policy_str); i++)
|
||||
if (i == aspm_policy)
|
||||
cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
|
||||
else
|
||||
cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
|
||||
return cnt;
|
||||
}
|
||||
|
||||
module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
|
||||
NULL, 0644);
|
||||
|
||||
#ifdef CONFIG_PCIEASPM_DEBUG
|
||||
static ssize_t link_state_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct pci_dev *pci_device = to_pci_dev(dev);
|
||||
struct pcie_link_state *link_state = pci_device->link_state;
|
||||
|
||||
return sprintf(buf, "%d\n", link_state->enabled_state);
|
||||
}
|
||||
|
||||
static ssize_t link_state_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf,
|
||||
size_t n)
|
||||
{
|
||||
struct pci_dev *pci_device = to_pci_dev(dev);
|
||||
int state;
|
||||
|
||||
if (n < 1)
|
||||
return -EINVAL;
|
||||
state = buf[0]-'0';
|
||||
if (state >= 0 && state <= 3) {
|
||||
/* setup link aspm state */
|
||||
pcie_aspm_configure_link_state(pci_device, state);
|
||||
return n;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static ssize_t clk_ctl_show(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct pci_dev *pci_device = to_pci_dev(dev);
|
||||
struct pcie_link_state *link_state = pci_device->link_state;
|
||||
|
||||
return sprintf(buf, "%d\n", link_state->clk_pm_enabled);
|
||||
}
|
||||
|
||||
static ssize_t clk_ctl_store(struct device *dev,
|
||||
struct device_attribute *attr,
|
||||
const char *buf,
|
||||
size_t n)
|
||||
{
|
||||
struct pci_dev *pci_device = to_pci_dev(dev);
|
||||
int state;
|
||||
|
||||
if (n < 1)
|
||||
return -EINVAL;
|
||||
state = buf[0]-'0';
|
||||
|
||||
down_read(&pci_bus_sem);
|
||||
mutex_lock(&aspm_lock);
|
||||
pcie_set_clock_pm(pci_device, !!state);
|
||||
mutex_unlock(&aspm_lock);
|
||||
up_read(&pci_bus_sem);
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
|
||||
static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
|
||||
|
||||
static char power_group[] = "power";
|
||||
void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
|
||||
{
|
||||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
return;
|
||||
|
||||
if (link_state->support_state)
|
||||
sysfs_add_file_to_group(&pdev->dev.kobj,
|
||||
&dev_attr_link_state.attr, power_group);
|
||||
if (link_state->clk_pm_capable)
|
||||
sysfs_add_file_to_group(&pdev->dev.kobj,
|
||||
&dev_attr_clk_ctl.attr, power_group);
|
||||
}
|
||||
|
||||
void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
|
||||
{
|
||||
struct pcie_link_state *link_state = pdev->link_state;
|
||||
|
||||
if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
|
||||
pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
|
||||
return;
|
||||
|
||||
if (link_state->support_state)
|
||||
sysfs_remove_file_from_group(&pdev->dev.kobj,
|
||||
&dev_attr_link_state.attr, power_group);
|
||||
if (link_state->clk_pm_capable)
|
||||
sysfs_remove_file_from_group(&pdev->dev.kobj,
|
||||
&dev_attr_clk_ctl.attr, power_group);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int __init pcie_aspm_disable(char *str)
|
||||
{
|
||||
aspm_disabled = 1;
|
||||
return 1;
|
||||
}
|
||||
|
||||
__setup("pcie_noaspm", pcie_aspm_disable);
|
||||
|
||||
static int __init pcie_aspm_init(void)
|
||||
{
|
||||
if (aspm_disabled)
|
||||
return 0;
|
||||
pci_osc_support_set(OSC_ACTIVE_STATE_PWR_SUPPORT|
|
||||
OSC_CLOCK_PWR_CAPABILITY_SUPPORT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fs_initcall(pcie_aspm_init);
|
||||
Reference in New Issue
Block a user