[IA64] Support irq migration across domain
Add support for IRQ migration across vector domain. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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Tony Luck
parent
4994be1b3f
commit
cd378f18cf
@ -354,11 +354,13 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask)
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irq &= (~IA64_IRQ_REDIRECTED);
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/* IRQ migration across domain is not supported yet */
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cpus_and(mask, mask, irq_to_domain(irq));
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cpus_and(mask, mask, cpu_online_map);
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if (cpus_empty(mask))
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return;
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if (reassign_irq_vector(irq, first_cpu(mask)))
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return;
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dest = cpu_physical_id(first_cpu(mask));
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if (list_empty(&iosapic_intr_info[irq].rtes))
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@ -376,6 +378,8 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask)
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else
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/* change delivery mode to fixed */
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low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
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low32 &= IOSAPIC_VECTOR_MASK;
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low32 |= irq_to_vector(irq);
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iosapic_intr_info[irq].low32 = low32;
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iosapic_intr_info[irq].dest = dest;
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@ -404,10 +408,20 @@ iosapic_end_level_irq (unsigned int irq)
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{
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ia64_vector vec = irq_to_vector(irq);
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struct iosapic_rte_info *rte;
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int do_unmask_irq = 0;
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if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
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do_unmask_irq = 1;
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mask_irq(irq);
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}
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move_native_irq(irq);
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list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
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iosapic_eoi(rte->iosapic->addr, vec);
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if (unlikely(do_unmask_irq)) {
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move_masked_irq(irq);
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unmask_irq(irq);
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}
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}
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#define iosapic_shutdown_level_irq mask_irq
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