Merge branch 'linus' into x86/cleanups
This commit is contained in:
Ingo Molnar
@@ -6,6 +6,13 @@
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <linux/clockchips.h>
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#include <asm/system.h>
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unsigned long idle_halt;
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EXPORT_SYMBOL(idle_halt);
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unsigned long idle_nomwait;
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EXPORT_SYMBOL(idle_nomwait);
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struct kmem_cache *task_xstate_cachep;
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@@ -45,6 +52,76 @@ void arch_task_cache_init(void)
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SLAB_PANIC, NULL);
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}
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/*
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* Idle related variables and functions
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*/
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unsigned long boot_option_idle_override = 0;
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EXPORT_SYMBOL(boot_option_idle_override);
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/*
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* Powermanagement idle function, if any..
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*/
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void (*pm_idle)(void);
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EXPORT_SYMBOL(pm_idle);
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#ifdef CONFIG_X86_32
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/*
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* This halt magic was a workaround for ancient floppy DMA
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* wreckage. It should be safe to remove.
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*/
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static int hlt_counter;
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void disable_hlt(void)
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{
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hlt_counter++;
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}
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EXPORT_SYMBOL(disable_hlt);
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void enable_hlt(void)
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{
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hlt_counter--;
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}
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EXPORT_SYMBOL(enable_hlt);
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static inline int hlt_use_halt(void)
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{
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return (!hlt_counter && boot_cpu_data.hlt_works_ok);
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}
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#else
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static inline int hlt_use_halt(void)
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{
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return 1;
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}
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#endif
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/*
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* We use this if we don't have any better
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* idle routine..
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*/
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void default_idle(void)
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{
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if (hlt_use_halt()) {
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current_thread_info()->status &= ~TS_POLLING;
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/*
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* TS_POLLING-cleared state must be visible before we
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* test NEED_RESCHED:
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*/
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smp_mb();
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if (!need_resched())
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safe_halt(); /* enables interrupts racelessly */
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else
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local_irq_enable();
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current_thread_info()->status |= TS_POLLING;
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} else {
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local_irq_enable();
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/* loop is done by the caller */
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cpu_relax();
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}
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}
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#ifdef CONFIG_APM_MODULE
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EXPORT_SYMBOL(default_idle);
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#endif
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static void do_nothing(void *unused)
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{
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}
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@@ -61,7 +138,7 @@ void cpu_idle_wait(void)
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{
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smp_mb();
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/* kick all the CPUs so that they exit out of pm_idle */
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smp_call_function(do_nothing, NULL, 0, 1);
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smp_call_function(do_nothing, NULL, 1);
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}
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EXPORT_SYMBOL_GPL(cpu_idle_wait);
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@@ -122,44 +199,129 @@ static void poll_idle(void)
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*
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* idle=mwait overrides this decision and forces the usage of mwait.
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*/
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#define MWAIT_INFO 0x05
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#define MWAIT_ECX_EXTENDED_INFO 0x01
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#define MWAIT_EDX_C1 0xf0
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static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
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{
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u32 eax, ebx, ecx, edx;
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if (force_mwait)
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return 1;
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if (c->x86_vendor == X86_VENDOR_AMD) {
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switch(c->x86) {
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case 0x10:
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case 0x11:
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return 0;
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if (c->cpuid_level < MWAIT_INFO)
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return 0;
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cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
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/* Check, whether EDX has extended info about MWAIT */
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if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
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return 1;
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/*
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* edx enumeratios MONITOR/MWAIT extensions. Check, whether
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* C1 supports MWAIT
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*/
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return (edx & MWAIT_EDX_C1);
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}
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/*
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* Check for AMD CPUs, which have potentially C1E support
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*/
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static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
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{
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if (c->x86_vendor != X86_VENDOR_AMD)
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return 0;
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if (c->x86 < 0x0F)
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return 0;
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/* Family 0x0f models < rev F do not have C1E */
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if (c->x86 == 0x0f && c->x86_model < 0x40)
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return 0;
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return 1;
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}
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/*
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* C1E aware idle routine. We check for C1E active in the interrupt
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* pending message MSR. If we detect C1E, then we handle it the same
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* way as C3 power states (local apic timer and TSC stop)
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*/
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static void c1e_idle(void)
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{
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static cpumask_t c1e_mask = CPU_MASK_NONE;
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static int c1e_detected;
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if (need_resched())
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return;
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if (!c1e_detected) {
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u32 lo, hi;
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rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
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if (lo & K8_INTP_C1E_ACTIVE_MASK) {
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c1e_detected = 1;
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mark_tsc_unstable("TSC halt in C1E");
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printk(KERN_INFO "System has C1E enabled\n");
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}
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}
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return 1;
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if (c1e_detected) {
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int cpu = smp_processor_id();
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if (!cpu_isset(cpu, c1e_mask)) {
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cpu_set(cpu, c1e_mask);
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/*
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* Force broadcast so ACPI can not interfere. Needs
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* to run with interrupts enabled as it uses
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* smp_function_call.
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*/
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local_irq_enable();
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
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&cpu);
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printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
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cpu);
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local_irq_disable();
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}
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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default_idle();
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/*
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* The switch back from broadcast mode needs to be
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* called with interrupts disabled.
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*/
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local_irq_disable();
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
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local_irq_enable();
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} else
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default_idle();
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}
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void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
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{
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static int selected;
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if (selected)
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return;
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#ifdef CONFIG_X86_SMP
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if (pm_idle == poll_idle && smp_num_siblings > 1) {
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printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
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" performance may degrade.\n");
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}
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#endif
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if (pm_idle)
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return;
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if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
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/*
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* Skip, if setup has overridden idle.
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* One CPU supports mwait => All CPUs supports mwait
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*/
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if (!pm_idle) {
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printk(KERN_INFO "using mwait in idle threads.\n");
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pm_idle = mwait_idle;
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}
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}
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selected = 1;
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printk(KERN_INFO "using mwait in idle threads.\n");
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pm_idle = mwait_idle;
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} else if (check_c1e_idle(c)) {
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printk(KERN_INFO "using C1E aware idle routine\n");
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pm_idle = c1e_idle;
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} else
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pm_idle = default_idle;
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}
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static int __init idle_setup(char *str)
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@@ -172,7 +334,27 @@ static int __init idle_setup(char *str)
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pm_idle = poll_idle;
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} else if (!strcmp(str, "mwait"))
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force_mwait = 1;
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else
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else if (!strcmp(str, "halt")) {
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/*
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* When the boot option of idle=halt is added, halt is
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* forced to be used for CPU idle. In such case CPU C2/C3
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* won't be used again.
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* To continue to load the CPU idle driver, don't touch
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* the boot_option_idle_override.
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*/
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pm_idle = default_idle;
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idle_halt = 1;
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return 0;
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} else if (!strcmp(str, "nomwait")) {
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/*
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* If the boot option of "idle=nomwait" is added,
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* it means that mwait will be disabled for CPU C2/C3
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* states. In such case it won't touch the variable
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* of boot_option_idle_override.
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*/
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idle_nomwait = 1;
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return 0;
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} else
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return -1;
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boot_option_idle_override = 1;
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