Merge branch 'drm-intel-fixes' into drm-intel-next
This commit is contained in:
@@ -1335,10 +1335,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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u32 reg;
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uint32_t DP = intel_dp->DP;
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/* Enable output, wait for it to become active */
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I915_WRITE(intel_dp->output_reg, intel_dp->DP);
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POSTING_READ(intel_dp->output_reg);
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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/*
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* On CPT we have to enable the port in training pattern 1, which
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* will happen below in intel_dp_set_link_train. Otherwise, enable
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* the port and wait for it to become active.
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*/
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if (!HAS_PCH_CPT(dev)) {
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I915_WRITE(intel_dp->output_reg, intel_dp->DP);
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POSTING_READ(intel_dp->output_reg);
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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}
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/* Write the link configuration data */
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intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
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@@ -1371,7 +1377,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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reg = DP | DP_LINK_TRAIN_PAT_1;
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if (!intel_dp_set_link_train(intel_dp, reg,
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DP_TRAINING_PATTERN_1))
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DP_TRAINING_PATTERN_1 |
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DP_LINK_SCRAMBLING_DISABLE))
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break;
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/* Set training pattern 1 */
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@@ -1446,7 +1453,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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/* channel eq pattern */
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if (!intel_dp_set_link_train(intel_dp, reg,
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DP_TRAINING_PATTERN_2))
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DP_TRAINING_PATTERN_2 |
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DP_LINK_SCRAMBLING_DISABLE))
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break;
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udelay(400);
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