[ARM] nommu: Initial uCLinux support for MMU-based CPUs
In noMMU mode, various of functions which are defined in mm/proc-*.S is not valid or needed to be avoided. i.g. switch_mm is not needed, just returns and this makes the I & D caches are valid which shows great improvement of performance including task switching and IPC. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King
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a4f7e76367
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@ -2,6 +2,7 @@
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* linux/arch/arm/mm/proc-v6.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Modified by Catalin Marinas for noMMU support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -88,6 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area)
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* - we are not using split page tables
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*/
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ENTRY(cpu_v6_switch_mm)
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#ifdef CONFIG_MMU
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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#ifdef CONFIG_SMP
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@ -97,6 +99,7 @@ ENTRY(cpu_v6_switch_mm)
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mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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#endif
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mov pc, lr
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/*
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@ -119,6 +122,7 @@ ENTRY(cpu_v6_switch_mm)
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* 1111 0 1 1 r/w r/w
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*/
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ENTRY(cpu_v6_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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bic r2, r1, #0x000003f0
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@ -145,6 +149,7 @@ ENTRY(cpu_v6_set_pte)
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str r2, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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#endif
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mov pc, lr
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@ -194,12 +199,14 @@ __v6_setup:
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r0, c2, c0, 2 @ TTB control register
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#ifdef CONFIG_SMP
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orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
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#endif
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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#endif /* CONFIG_MMU */
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#ifdef CONFIG_VFP
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mrc p15, 0, r0, c1, c0, 2
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orr r0, r0, #(0xf << 20)
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