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OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change

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Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency.  Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Paul Walmsley
2009-06-19 19:08:27 -06:00
committed by paul
parent c9812d042a
commit d0ba3922ae
4 changed files with 14 additions and 8 deletions
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4
arch/arm/plat-omap/include/mach/sram.h
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@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll, u32 f);
u32 unlock_dll, u32 f, u32 sdrc_mr);
/* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll, u32 f);
u32 unlock_dll, u32 f, u32 sdrc_mr);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif