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MIPS: TXx9: Cache fixup

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TX39/TX49 can enable/disable I/D cache at runtime.  Add kernel options
to control them.  This is useful to debug some cache-related issues,
such as aliasing or I/D coherency.  Also enable CWF bit for TX49 SoCs.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
2008-08-19 22:55:09 +09:00
committed by Ralf Baechle
parent 860e546c19
commit d10e025f0e
6 changed files with 124 additions and 26 deletions
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18
arch/mips/txx9/generic/setup_tx3927.c
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@ -99,16 +99,14 @@ void __init tx3927_setup(void)
txx9_gpio_init(TX3927_PIO_REG, 0, 16);
conf = read_c0_conf();
if (!(conf & TX39_CONF_ICE))
printk(KERN_INFO "TX3927 I-Cache disabled.\n");
if (!(conf & TX39_CONF_DCE))
printk(KERN_INFO "TX3927 D-Cache disabled.\n");
else if (!(conf & TX39_CONF_WBON))
printk(KERN_INFO "TX3927 D-Cache WriteThrough.\n");
else if (!(conf & TX39_CONF_CWFON))
printk(KERN_INFO "TX3927 D-Cache WriteBack.\n");
else
printk(KERN_INFO "TX3927 D-Cache WriteBack (CWF) .\n");
if (conf & TX39_CONF_DCE) {
if (!(conf & TX39_CONF_WBON))
pr_info("TX3927 D-Cache WriteThrough.\n");
else if (!(conf & TX39_CONF_CWFON))
pr_info("TX3927 D-Cache WriteBack.\n");
else
pr_info("TX3927 D-Cache WriteBack (CWF) .\n");
}
}
void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)