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drm/nva0/clk: fix accidental limiting of pll coefficients

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
2013-10-22 13:45:16 +10:00
parent 75faef78c9
commit d29b992470
1 changed files with 16 additions and 13 deletions
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29
drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c
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@@ -38,7 +38,7 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
* "clk" parameter in kHz * "clk" parameter in kHz
* returns calculated clock * returns calculated clock
*/ */
int cv = nouveau_bios(subdev)->version.chip; struct nouveau_bios *bios = nouveau_bios(subdev);
int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq; int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;
int minM = info->vco1.min_m, maxM = info->vco1.max_m; int minM = info->vco1.min_m, maxM = info->vco1.max_m;
int minN = info->vco1.min_n, maxN = info->vco1.max_n; int minN = info->vco1.min_n, maxN = info->vco1.max_n;
@@ -54,18 +54,21 @@ getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
/* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */ /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
/* possibly correlated with introduction of 27MHz crystal */ /* possibly correlated with introduction of 27MHz crystal */
if (cv < 0x17 || cv == 0x1a || cv == 0x20) { if (bios->version.major < 0x60) {
if (clk > 250000) int cv = bios->version.chip;
maxM = 6; if (cv < 0x17 || cv == 0x1a || cv == 0x20) {
if (clk > 340000) if (clk > 250000)
maxM = 2; maxM = 6;
} else if (cv < 0x40) { if (clk > 340000)
if (clk > 150000) maxM = 2;
maxM = 6; } else if (cv < 0x40) {
if (clk > 200000) if (clk > 150000)
maxM = 4; maxM = 6;
if (clk > 340000) if (clk > 200000)
maxM = 2; maxM = 4;
if (clk > 340000)
maxM = 2;
}
} }
P = 1 << maxP; P = 1 << maxP;