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davinci: da8xx/omapl1: add support for the second sysconfig module

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OMAP-L138 adds a second SYSCFG region having useful functionality
like deep sleep, pull up/down control and SATA clock stop.

This patch makes provision for accessing registers from second
SYSCFG region in da8xx code.

Note that OMAP-L137 has a single SYSCFG region.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sekhar Nori
2009-11-16 17:21:32 +05:30
committed by Kevin Hilman
parent f2a4c59df6
commit d2de05827c
6 changed files with 28 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-davinci/board-da830-evm.c
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@@ -112,7 +112,7 @@ static __init void da830_evm_usb_init(void)
* Set up USB clock/mode in the CFGCHIP2 register. * Set up USB clock/mode in the CFGCHIP2 register.
* FYI: CFGCHIP2 is 0x0000ef00 initially. * FYI: CFGCHIP2 is 0x0000ef00 initially.
*/ */
cfgchip2 = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG)); cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
/* USB2.0 PHY reference clock is 24 MHz */ /* USB2.0 PHY reference clock is 24 MHz */
cfgchip2 &= ~CFGCHIP2_REFFREQ; cfgchip2 &= ~CFGCHIP2_REFFREQ;
@@ -139,7 +139,7 @@ static __init void da830_evm_usb_init(void)
cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN; cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
#endif #endif
__raw_writel(cfgchip2, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG)); __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
/* USB_REFCLKIN is not used. */ /* USB_REFCLKIN is not used. */
ret = davinci_cfg_reg(DA830_USB0_DRVVBUS); ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);

2
arch/arm/mach-davinci/board-da850-evm.c
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@@ -537,7 +537,7 @@ static int __init da850_evm_config_emac(void)
if (!machine_is_davinci_da850_evm()) if (!machine_is_davinci_da850_evm())
return 0; return 0;
cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG); cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
val = __raw_readl(cfg_chip3_base); val = __raw_readl(cfg_chip3_base);

8
arch/arm/mach-davinci/da830.c
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@@ -1208,13 +1208,13 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
void __init da830_init(void) void __init da830_init(void)
{ {
da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K); da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module")) if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
return; return;
davinci_soc_info_da830.jtag_id_base = davinci_soc_info_da830.jtag_id_base =
DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG); DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG_VIRT(0x120); davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
davinci_common_init(&davinci_soc_info_da830); davinci_common_init(&davinci_soc_info_da830);
} }

20
arch/arm/mach-davinci/da850.c
View File

@@ -838,12 +838,12 @@ static void da850_set_async3_src(int pllnum)
} }
} }
v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG)); v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
if (pllnum) if (pllnum)
v |= CFGCHIP3_ASYNC3_CLKSRC; v |= CFGCHIP3_ASYNC3_CLKSRC;
else else
v &= ~CFGCHIP3_ASYNC3_CLKSRC; v &= ~CFGCHIP3_ASYNC3_CLKSRC;
__raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG)); __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
} }
#ifdef CONFIG_CPU_FREQ #ifdef CONFIG_CPU_FREQ
@@ -996,9 +996,9 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
postdiv = opp->postdiv; postdiv = opp->postdiv;
/* Unlock writing to PLL registers */ /* Unlock writing to PLL registers */
v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG)); v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
v &= ~CFGCHIP0_PLL_MASTER_LOCK; v &= ~CFGCHIP0_PLL_MASTER_LOCK;
__raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG)); __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
ret = davinci_set_pllrate(pll, prediv, mult, postdiv); ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
if (WARN_ON(ret)) if (WARN_ON(ret))
@@ -1053,13 +1053,17 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
void __init da850_init(void) void __init da850_init(void)
{ {
da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K); da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module")) if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
return;
da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
return; return;
davinci_soc_info_da850.jtag_id_base = davinci_soc_info_da850.jtag_id_base =
DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG); DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120); davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
davinci_common_init(&davinci_soc_info_da850); davinci_common_init(&davinci_soc_info_da850);

3
arch/arm/mach-davinci/devices-da8xx.c
View File

@@ -42,7 +42,8 @@
#define DA8XX_MDIO_REG_OFFSET 0x4000 #define DA8XX_MDIO_REG_OFFSET 0x4000
#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
void __iomem *da8xx_syscfg_base; void __iomem *da8xx_syscfg0_base;
void __iomem *da8xx_syscfg1_base;
static struct plat_serial8250_port da8xx_serial_pdata[] = { static struct plat_serial8250_port da8xx_serial_pdata[] = {
{ {

10
arch/arm/mach-davinci/include/mach/da8xx.h
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@@ -21,7 +21,8 @@
#include <mach/mmc.h> #include <mach/mmc.h>
#include <mach/usb.h> #include <mach/usb.h>
extern void __iomem *da8xx_syscfg_base; extern void __iomem *da8xx_syscfg0_base;
extern void __iomem *da8xx_syscfg1_base;
/* /*
* The cp_intc interrupt controller for the da8xx isn't in the same * The cp_intc interrupt controller for the da8xx isn't in the same
@@ -34,13 +35,16 @@ extern void __iomem *da8xx_syscfg_base;
#define DA8XX_CP_INTC_SIZE SZ_8K #define DA8XX_CP_INTC_SIZE SZ_8K
#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) #define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
#define DA8XX_SYSCFG_BASE (IO_PHYS + 0x14000) #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
#define DA8XX_SYSCFG_VIRT(x) (da8xx_syscfg_base + (x)) #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
#define DA8XX_JTAG_ID_REG 0x18 #define DA8XX_JTAG_ID_REG 0x18
#define DA8XX_CFGCHIP0_REG 0x17c #define DA8XX_CFGCHIP0_REG 0x17c
#define DA8XX_CFGCHIP2_REG 0x184 #define DA8XX_CFGCHIP2_REG 0x184
#define DA8XX_CFGCHIP3_REG 0x188 #define DA8XX_CFGCHIP3_REG 0x188
#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
#define DA8XX_PSC0_BASE 0x01c10000 #define DA8XX_PSC0_BASE 0x01c10000
#define DA8XX_PLL0_BASE 0x01c11000 #define DA8XX_PLL0_BASE 0x01c11000
#define DA8XX_TIMER64P0_BASE 0x01c20000 #define DA8XX_TIMER64P0_BASE 0x01c20000