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staging: rtl8192e: Prepare header files to ease use of typedef enum conversion

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The tool that I am using fails for certain conditions. This patch makes trivial
changes to the source to allow the tool to work for all cases.

I also remove some artifacts left from the typedef struct conversion.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
This commit is contained in:
Larry Finger
2011-07-19 12:50:41 -05:00
parent 66ba443abf
commit d3b2c17251
10 changed files with 136 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/staging/rtl8192e/r8190P_def.h
View File

@@ -29,7 +29,7 @@
#define RX_CMD_QUEUE 1
typedef enum _rtl819x_loopback{
typedef enum _rtl819x_loopback_e{
RTL819X_NO_LOOPBACK = 0,
RTL819X_MAC_LOOPBACK = 1,
RTL819X_DMA_LOOPBACK = 2,
@@ -178,7 +178,7 @@ struct bb_reg_definition {
u32 rfTxAFE;
u32 rfLSSIReadBack;
u32 rfLSSIReadBackPi;
};//, *struct bb_reg_definition *;
};
struct tx_fwinfo {
u8 TxRate:7;
@@ -205,7 +205,7 @@ struct tx_fwinfo {
u32 TxAGCSign:1;
u32 Tx_INFO_RSVD:6;
u32 PacketID:13;
};//;
};
struct tx_fwinfo_8190pci {
u8 TxRate:7;
@@ -237,7 +237,7 @@ struct tx_fwinfo_8190pci {
u32 PacketID:13;
};//, *struct tx_fwinfo_8190pci *;
};
#define TX_DESC_SIZE 32
@@ -276,7 +276,7 @@ struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
u8 rxsc:2;
u8 sgi_en:1;
u8 ex_intf_flag:1;
};//;
};
struct phy_sts_ofdm_819xpci {
u8 trsw_gain_X[4];
@@ -292,13 +292,13 @@ struct phy_sts_ofdm_819xpci {
u8 max_ex_pwr;
u8 sgi_en;
u8 rxsc_sgien_exflg;
};//;
};
struct phy_sts_cck_819xpci {
u8 adc_pwdb_X[4];
u8 sq_rpt;
u8 cck_agc_rpt;
};//;
};
#define PHY_RSSI_SLID_WIN_MAX 100
@@ -340,7 +340,7 @@ struct tx_desc {
u32 Reserved5;
u32 Reserved6;
u32 Reserved7;
};//, *ptx_desc;
};
struct tx_desc_cmd {
@@ -364,7 +364,7 @@ struct tx_desc_cmd {
u32 Reserved4;
u32 Reserved5;
u32 Reserved6;
};//, *ptx_desc_cmd;
};
struct rx_desc {
u16 Length:14;
@@ -385,7 +385,7 @@ struct rx_desc {
u32 BufferAddress;
};//, *prx_desc;
};
struct rx_fwinfo {
@@ -407,6 +407,6 @@ struct rx_fwinfo {
u32 TSFL;
};//, *prx_fwinfo;
};
#endif

10
drivers/staging/rtl8192e/r8192E_cmdpkt.h
View File

@@ -55,14 +55,14 @@ struct cmpk_txfb {
u16 reserve3; /* */
u16 duration; /* */
};//;
};
struct cmpk_intr_sta {
u8 element_id;
u8 length;
u16 reserve;
u32 interrupt_status;
};//;
};
struct cmpk_set_cfg {
@@ -79,7 +79,7 @@ struct cmpk_set_cfg {
u8 cfg_offset;
u32 value;
u32 mask;
};//;
};
#define cmpk_query_cfg_t struct cmpk_set_cfg
@@ -118,7 +118,7 @@ struct cmpk_rx_dbginfo {
u8 element_id;
};//;
};
struct cmpk_tx_rahis {
u8 element_id;
@@ -137,7 +137,7 @@ struct cmpk_tx_rahis {
} __packed;
typedef enum tag_command_packet_directories
typedef enum _cmpk_element_e
{
RX_TX_FEEDBACK = 0,
RX_INTERRUPT_STATUS = 1,

10
drivers/staging/rtl8192e/r8192E_firmware.h
View File

@@ -23,13 +23,13 @@
#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 )
typedef enum _firmware_init_step{
typedef enum _firmware_init_step_e{
FW_INIT_STEP0_BOOT = 0,
FW_INIT_STEP1_MAIN = 1,
FW_INIT_STEP2_DATA = 2,
} firmware_init_step_e;
typedef enum _opt_rst_type{
typedef enum _opt_rst_type_e{
OPT_SYSTEM_RESET = 0,
OPT_FIRMWARE_RESET = 1,
} opt_rst_type_e;
@@ -39,12 +39,12 @@ typedef enum _desc_packet_type_e{
DESC_PACKET_TYPE_NORMAL = 1,
} desc_packet_type_e;
typedef enum _firmware_source{
typedef enum _firmware_source_e{
FW_SOURCE_IMG_FILE = 0,
FW_SOURCE_HEADER_FILE = 1,
} firmware_source_e, *pfirmware_source_e;
typedef enum _firmware_status{
typedef enum _firmware_status_e{
FW_STATUS_0_INIT = 0,
FW_STATUS_1_MOVE_BOOT_CODE = 1,
FW_STATUS_2_MOVE_MAIN_CODE = 2,
@@ -56,7 +56,7 @@ typedef enum _firmware_status{
struct fw_seg_container {
u16 seg_size;
u8 *seg_ptr;
};//, *pfw_seg_container;
};
struct rt_firmware {
firmware_status_e firmware_status;

4
drivers/staging/rtl8192e/r8192E_phy.h
View File

@@ -73,7 +73,7 @@ extern u32 rtl819XRadioB_Array[];
extern u32 rtl819XRadioC_Array[];
extern u32 rtl819XRadioD_Array[];
typedef enum _HW90_BLOCK {
typedef enum _HW90_BLOCK_E {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
@@ -81,7 +81,7 @@ typedef enum _HW90_BLOCK {
HW90_BLOCK_MAXIMUM = 4,
} HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF90_RADIO_PATH{
typedef enum _RF90_RADIO_PATH_E{
RF90_PATH_A = 0,
RF90_PATH_B = 1,
RF90_PATH_C = 2,

18
drivers/staging/rtl8192e/rtl819x_HT.h
View File

@@ -327,7 +327,7 @@ struct rt_htinfo_sta_entry {
u16 nAMSDU_MaxSize;
};//, *struct rt_htinfo_sta_entry *;
};
@@ -359,12 +359,12 @@ struct mimo_rssi {
u32 AntennaC;
u32 AntennaD;
u32 Average;
};//, *struct mimo_rssi *;
};
struct mimo_evm {
u32 EVM1;
u32 EVM2;
};//, *struct mimo_evm *;
};
struct false_alarm_stats {
u32 Cnt_Parity_Fail;
@@ -374,7 +374,7 @@ struct false_alarm_stats {
u32 Cnt_Ofdm_fail;
u32 Cnt_Cck_fail;
u32 Cnt_all;
};//, *struct false_alarm_stats *;
};
extern u8 MCS_FILTER_ALL[16];
@@ -397,14 +397,14 @@ extern u8 MCS_FILTER_1SS[16];
#define IS_11N_MCS_RATE(rate) (rate&0x80)
typedef enum _HT_AGGRE_SIZE{
typedef enum _HT_AGGRE_SIZE_E{
HT_AGG_SIZE_8K = 0,
HT_AGG_SIZE_16K = 1,
HT_AGG_SIZE_32K = 2,
HT_AGG_SIZE_64K = 3,
} HT_AGGRE_SIZE_E, *PHT_AGGRE_SIZE_E;
typedef enum _HT_IOT_PEER
typedef enum _HT_IOT_PEER_E
{
HT_IOT_PEER_UNKNOWN = 0,
HT_IOT_PEER_REALTEK = 1,
@@ -420,12 +420,12 @@ typedef enum _HT_IOT_PEER
HT_IOT_PEER_MAX = 11,
} HT_IOT_PEER_E, *PHTIOT_PEER_E;
typedef enum _HT_IOT_PEER_SUBTYPE
typedef enum _HT_IOT_PEER_SUBTYPE_E
{
HT_IOT_PEER_ATHEROS_DIR635 = 0,
} HT_IOT_PEER_SUBTYPE_E, *PHTIOT_PEER_SUBTYPE_E;
typedef enum _HT_IOT_ACTION{
typedef enum _HT_IOT_ACTION_E{
HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
@@ -466,7 +466,7 @@ typedef enum _HT_IOT_RAFUNC{
HT_IOT_RAFUNC_TX_AMSDU = 0x02,
} HT_IOT_RAFUNC, *PHT_IOT_RAFUNC;
typedef enum _RT_HT_CAP{
typedef enum _RT_HT_CAPBILITY{
RT_HT_CAP_USE_TURBO_AGGR = 0x01,
RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
RT_HT_CAP_USE_AMPDU = 0x04,

10
drivers/staging/rtl8192e/rtl819x_Qos.h
View File

@@ -107,7 +107,7 @@ struct wmm_tspec {
struct octet_string {
u8 *Octet;
u16 Length;
};//, *struct octet_string *;
};
#define MAX_WMMELE_LENGTH 64
typedef u32 QOS_MODE, *PQOS_MODE;
@@ -165,7 +165,7 @@ typedef enum _ACK_POLICY{
#define GET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart) LE_BITS_TO_1BYTE(_pStart, 5, 2)
#define SET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart, _val) SET_BITS_TO_LE_1BYTE(_pStart, 5, 2, _val)
typedef enum {
typedef enum _QOSIE_SOURCE{
QOSIE_SRC_ADDTSREQ,
QOSIE_SRC_ADDTSRSP,
QOSIE_SRC_REASOCREQ,
@@ -233,7 +233,7 @@ struct acm {
u64 UsedTime;
u64 MediumTime;
u8 HwAcmCtl;
};//, *struct acm *;
};
@@ -343,7 +343,7 @@ struct sta_qos {
bool bEnableRxImmBA;
};//, *struct sta_qos *;
};
#define QBSS_LOAD_SIZE 5
#define GET_QBSS_LOAD_STA_COUNT(__pStart) ReadEF2Byte(__pStart)
@@ -366,7 +366,7 @@ struct bss_qos {
u8 QBssLoad[QBSS_LOAD_SIZE];
bool bQBssLoadValid;
};//, *struct bss_qos *;
};
#define sQoSCtlLng 2
#define QOS_CTRL_LEN(_QosMode) ( (_QosMode > QOS_DISABLE)? sQoSCtlLng : 0 )

14
drivers/staging/rtl8192e/rtl_core.h
View File

@@ -240,7 +240,7 @@ enum RTL_DEBUG {
COMP_ERR = BIT31
};
typedef enum{
typedef enum _nic_t{
NIC_UNKNOWN = 0,
NIC_8192E = 1,
NIC_8190P = 2,
@@ -257,7 +257,7 @@ typedef enum _RT_EEPROM_TYPE{
EEPROM_BOOT_EFUSE,
} RT_EEPROM_TYPE,*PRT_EEPROM_TYPE;
typedef enum _tag_TxCmd_Config_Index{
typedef enum _DCMD_TXCMD_OP{
TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
@@ -276,7 +276,7 @@ typedef enum _RT_RF_TYPE_819xU{
RF_PSEUDO_11N = 5,
} RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
typedef enum tag_Rf_Operatetion_State
typedef enum _RF_STEP_E
{
RF_STEP_INIT = 0,
RF_STEP_NORMAL,
@@ -360,20 +360,20 @@ struct rtl_reg_debug {
unsigned char length;
} head;
unsigned char buf[0xff];
};//;
};
struct rt_tx_rahis {
u32 cck[4];
u32 ofdm[8];
u32 ht_mcs[4][16];
};//, *prt_tx_rahis_t;
};
struct rt_smooth_data_4rf {
char elements[4][100];
u32 index;
u32 TotalNum;
u32 TotalVal[4];
};//, *struct rt_smooth_data_4rf *;
};
struct rt_stats {
unsigned long txrdu;
@@ -1015,7 +1015,7 @@ struct r8192_priv {
u8 H2CTxCmdSeq;
};//;
};
extern const struct ethtool_ops rtl819x_ethtool_ops;

2
drivers/staging/rtl8192e/rtl_debug.h
View File

@@ -43,7 +43,7 @@ struct net_device;
printk Fmt; \
}
typedef enum tag_DBGP_Flag_Type_Definition
typedef enum _DBGP_FLAG_E
{
FQoS = 0,
FTX = 1,

31
drivers/staging/rtl8192e/rtl_dm.h
View File

@@ -125,9 +125,9 @@ struct dig_t {
bool initialgain_lowerbound_state;
long rssi_val;
};//;
};
typedef enum tag_dynamic_init_gain_state_definition
typedef enum _dm_dig_sta_e
{
DM_STA_DIG_OFF = 0,
DM_STA_DIG_ON,
@@ -135,7 +135,7 @@ typedef enum tag_dynamic_init_gain_state_definition
} dm_dig_sta_e;
typedef enum tag_dynamic_ratr_state_definition
typedef enum _dm_ratr_sta_e
{
DM_RATR_STA_HIGH = 0,
DM_RATR_STA_MIDDLE = 1,
@@ -143,7 +143,7 @@ typedef enum tag_dynamic_ratr_state_definition
DM_RATR_STA_MAX
} dm_ratr_sta_e;
typedef enum tag_dynamic_init_gain_operation_type_definition
typedef enum _dm_dig_op_e
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
@@ -161,7 +161,7 @@ typedef enum tag_dynamic_init_gain_operation_type_definition
DIG_OP_TYPE_MAX
} dm_dig_op_e;
typedef enum tag_dig_algorithm_definition
typedef enum _dm_dig_alg_e
{
DIG_ALGO_BY_FALSE_ALARM = 0,
DIG_ALGO_BY_RSSI = 1,
@@ -170,14 +170,14 @@ typedef enum tag_dig_algorithm_definition
DIG_ALGO_MAX
} dm_dig_alg_e;
typedef enum tag_DIG_TWO_PORT_ALGO_Definition
typedef enum _DM_DIG_TWO_PORT_ALG_E
{
DIG_TWO_PORT_ALGO_RSSI = 0,
DIG_TWO_PORT_ALGO_FALSE_ALARM = 1,
} DM_DIG_TWO_PORT_ALG_E;
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
typedef enum _DM_DIG_EXT_PORT_ALG_E
{
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
@@ -186,14 +186,14 @@ typedef enum tag_DIG_EXT_PORT_ALGO_Definition
DIG_EXT_PORT_STAGE_MAX = 4,
} DM_DIG_EXT_PORT_ALG_E;
typedef enum tag_dig_dbgmode_definition
typedef enum _dm_dig_dbg_e
{
DIG_DBG_OFF = 0,
DIG_DBG_ON = 1,
DIG_DBG_MAX
} dm_dig_dbg_e;
typedef enum tag_dig_connect_definition
typedef enum _dm_dig_connect_e
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
@@ -204,7 +204,7 @@ typedef enum tag_dig_connect_definition
DIG_CONNECT_MAX
} dm_dig_connect_e;
typedef enum tag_dig_packetdetection_threshold_definition
typedef enum _dm_dig_pd_th_e
{
DIG_PD_AT_LOW_POWER = 0,
DIG_PD_AT_NORMAL_POWER = 1,
@@ -212,12 +212,13 @@ typedef enum tag_dig_packetdetection_threshold_definition
DIG_PD_MAX
} dm_dig_pd_th_e;
typedef enum tag_dig_cck_cs_ratio_state_definition
typedef enum _dm_dig_cs_ratio_e
{
DIG_CS_RATIO_LOWER = 0,
DIG_CS_RATIO_HIGHER = 1,
DIG_CS_MAX
} dm_dig_cs_ratio_e;
struct drx_path_sel {
u8 Enable;
u8 DbgMode;
@@ -232,9 +233,9 @@ struct drx_path_sel {
u8 rf_rssi[4];
u8 rf_enable_rssi_th[4];
long cck_pwdb_sta[4];
};//;
};
typedef enum tag_CCK_Rx_Path_Method_Definition
typedef enum _DM_CCK_Rx_Path_Method
{
CCK_Rx_Version_1 = 0,
CCK_Rx_Version_2= 1,
@@ -242,7 +243,7 @@ typedef enum tag_CCK_Rx_Path_Method_Definition
} DM_CCK_Rx_Path_Method;
typedef enum tag_DM_DbgMode_Definition
typedef enum _DM_DBG_E
{
DM_DBG_OFF = 0,
DM_DBG_ON = 1,
@@ -253,7 +254,7 @@ struct dcmd_txcmd {
u32 Op;
u32 Length;
u32 Value;
};//, *struct dcmd_txcmd *;
};
/*------------------------------Define structure----------------------------*/

23
drivers/staging/rtl8192e/rtllib.h
View File

@@ -200,7 +200,7 @@ struct cb_desc {
u8 bBTTxPacket;
u8 bIsBTProbRsp;
};//, *pcb_desc;
};
/*--------------------------Define -------------------------------------------*/
#define MGN_1M 0x02
@@ -482,7 +482,7 @@ struct ieee_param {
u8 key[0];
} crypt;
} u;
};//;
};
#if WIRELESS_EXT < 17
@@ -620,6 +620,7 @@ typedef enum _InitialGainOpType{
IG_Restore,
IG_Max
} InitialGainOpType;
typedef enum _LED_CTL_MODE{
LED_CTL_POWER_ON = 1,
LED_CTL_LINK = 2,
@@ -656,7 +657,7 @@ typedef enum _WIRELESS_MODE {
WIRELESS_MODE_N_5G = 0x20
} WIRELESS_MODE;
typedef enum _NETWORK_TYPE{
typedef enum _WIRELESS_NETWORK_TYPE{
WIRELESS_11B = 1,
WIRELESS_11G = 2,
WIRELESS_11A = 4,
@@ -1775,14 +1776,14 @@ enum rtllib_state {
struct tx_pending {
int frag;
struct rtllib_txb *txb;
};//;
};
struct bandwidth_autoswitch {
long threshold_20Mhzto40Mhz;
long threshold_40Mhzto20Mhz;
bool bforced_tx20Mhz;
bool bautoswitch_enable;
};//,*pbandwidth_autoswitch;
};
@@ -1823,7 +1824,7 @@ typedef enum _RT_JOIN_ACTION{
struct ibss_parms {
u16 atimWin;
};//, *struct ibss_parms *;
};
#define MAX_NUM_RATES 264
typedef enum _RT_RF_POWER_STATE
@@ -1853,7 +1854,7 @@ struct rt_pm_wol_info {
u16 CrcRemainder;
u8 WFMIndex;
WOLPATTERN_TYPE PatternType;
};//, *struct rt_pm_wol_info *;
};
struct rt_pwr_save_ctrl {
@@ -1912,7 +1913,7 @@ struct rt_pwr_save_ctrl {
u8 oWLANMode;
struct rt_pm_wol_info PmWoLPatternInfo[MAX_SUPPORT_WOL_PATTERN_NUM];
};//,*struct rt_pwr_save_ctrl *;
};
typedef u32 RT_RF_CHANGE_SOURCE;
#define RF_CHANGE_BY_SW BIT31
@@ -1921,7 +1922,7 @@ typedef u32 RT_RF_CHANGE_SOURCE;
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_INIT 0
typedef enum
typedef enum _country_code_type_t
{
COUNTRY_CODE_FCC = 0,
COUNTRY_CODE_IC = 1,
@@ -2000,7 +2001,7 @@ struct rt_link_detect {
u32 NumTxUnicastOkInPeriod;
u32 LastNumTxUnicast;
u32 LastNumRxUnicast;
};//, *struct rt_link_detect *;
};
struct sw_cam_table {
@@ -2011,7 +2012,7 @@ struct sw_cam_table {
u8 useDK;
u8 key_index;
};//,*struct sw_cam_table *;
};
#define TOTAL_CAM_ENTRY 32
struct rate_adaptive {
u8 rate_adaptive_disabled;