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[PATCH] sky2: spelling fixes

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Cosmetic cleanup's: mostly spelling fixes etc.

Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
shemminger@osdl.org
2005-10-26 12:16:09 -07:00
committed by Jeff Garzik
parent b2f5ad4fec
commit d571b694df
2 changed files with 21 additions and 21 deletions
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32
drivers/net/sky2.c
View File

@@ -214,7 +214,7 @@ static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1); pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
/* looks like this xl is back asswards .. */ /* looks like this XL is back asswards .. */
if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
reg1 |= PCI_Y2_PHY1_COMA; reg1 |= PCI_Y2_PHY1_COMA;
if (hw->ports > 1) if (hw->ports > 1)
@@ -461,7 +461,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
if (ledover) if (ledover)
gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
/* Enable phy interrupt on autonegotiation complete (or link up) */ /* Enable phy interrupt on auto-negotiation complete (or link up) */
if (sky2->autoneg == AUTONEG_ENABLE) if (sky2->autoneg == AUTONEG_ENABLE)
gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
else else
@@ -578,10 +578,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T), sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
GMF_RX_CTRL_DEF); GMF_RX_CTRL_DEF);
/* Flush Rx MAC FIFO on any flowcontrol or error */ /* Flush Rx MAC FIFO on any flow control or error */
reg = GMR_FS_ANY_ERR; reg = GMR_FS_ANY_ERR;
if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1) if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
reg = 0; /* WA Dev #4115 */ reg = 0; /* WA dev #4.115 */
sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg); sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
/* Set threshold to 0xa (64 bytes) /* Set threshold to 0xa (64 bytes)
@@ -662,7 +662,7 @@ static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
} }
/* /*
* This is a workaround code taken from syskonnect sk98lin driver * This is a workaround code taken from SysKonnect sk98lin driver
* to deal with chip bug on Yukon EC rev 0 in the wraparound case. * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
*/ */
static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
@@ -785,7 +785,7 @@ stopped:
sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
} }
/* Cleanout receive buffer area, assumes receiver hardware stopped */ /* Clean out receive buffer area, assumes receiver hardware stopped */
static void sky2_rx_clean(struct sky2_port *sky2) static void sky2_rx_clean(struct sky2_port *sky2)
{ {
unsigned i; unsigned i;
@@ -1174,7 +1174,7 @@ out_unlock:
* Free ring elements from starting at tx_cons until "done" * Free ring elements from starting at tx_cons until "done"
* *
* NB: the hardware will tell us about partial completion of multi-part * NB: the hardware will tell us about partial completion of multi-part
* buffers; these are defered until completion. * buffers; these are deferred until completion.
*/ */
static void sky2_tx_complete(struct sky2_port *sky2, u16 done) static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
{ {
@@ -1182,7 +1182,7 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
unsigned i; unsigned i;
if (unlikely(netif_msg_tx_done(sky2))) if (unlikely(netif_msg_tx_done(sky2)))
printk(KERN_DEBUG "%s: tx done, upto %u\n", printk(KERN_DEBUG "%s: tx done, up to %u\n",
dev->name, done); dev->name, done);
spin_lock(&sky2->tx_lock); spin_lock(&sky2->tx_lock);
@@ -1282,7 +1282,7 @@ static int sky2_down(struct net_device *dev)
sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
/* turn off led's */ /* turn off LED's */
sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
sky2_tx_clean(sky2); sky2_tx_clean(sky2);
@@ -1364,7 +1364,7 @@ static void sky2_link_up(struct sky2_port *sky2)
if (netif_msg_link(sky2)) if (netif_msg_link(sky2))
printk(KERN_INFO PFX printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n", "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
sky2->netdev->name, sky2->speed, sky2->netdev->name, sky2->speed,
sky2->duplex == DUPLEX_FULL ? "full" : "half", sky2->duplex == DUPLEX_FULL ? "full" : "half",
(sky2->tx_pause && sky2->rx_pause) ? "both" : (sky2->tx_pause && sky2->rx_pause) ? "both" :
@@ -1451,7 +1451,7 @@ static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
} }
/* /*
* Interrrupt from PHY are handled in tasklet (soft irq) * Interrupt from PHY are handled in tasklet (soft irq)
* because accessing phy registers requires spin wait which might * because accessing phy registers requires spin wait which might
* cause excess interrupt latency. * cause excess interrupt latency.
*/ */
@@ -1556,7 +1556,7 @@ static int sky2_change_mtu(struct net_device *dev, int new_mtu)
/* /*
* Receive one packet. * Receive one packet.
* For small packets or errors, just reuse existing skb. * For small packets or errors, just reuse existing skb.
* For larger pakects, get new buffer. * For larger packets, get new buffer.
*/ */
static struct sk_buff *sky2_receive(struct sky2_port *sky2, static struct sk_buff *sky2_receive(struct sky2_port *sky2,
u16 length, u32 status) u16 length, u32 status)
@@ -1818,7 +1818,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
} }
if (status & Y2_IS_PCI_EXP) { if (status & Y2_IS_PCI_EXP) {
/* PCI-Express uncorrectable Error occured */ /* PCI-Express uncorrectable Error occurred */
u32 pex_err; u32 pex_err;
pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
@@ -2113,7 +2113,7 @@ static int sky2_reset(struct sky2_hw *hw)
if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10); sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
else /* WA 4109 */ else /* WA dev 4.109 */
sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04); sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190); sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
@@ -2420,7 +2420,7 @@ static void sky2_set_multicast(struct net_device *dev)
reg = gma_read16(hw, port, GM_RX_CTRL); reg = gma_read16(hw, port, GM_RX_CTRL);
reg |= GM_RXCR_UCF_ENA; reg |= GM_RXCR_UCF_ENA;
if (dev->flags & IFF_PROMISC) /* promiscious */ if (dev->flags & IFF_PROMISC) /* promiscuous */
reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
memset(filter, 0xff, sizeof(filter)); memset(filter, 0xff, sizeof(filter));
@@ -2833,7 +2833,7 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
} }
} }
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
/* byte swap decriptors in hardware */ /* byte swap descriptors in hardware */
{ {
u32 reg; u32 reg;

10
drivers/net/sky2.h
View File

@@ -356,11 +356,11 @@ enum {
/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
enum { enum {
Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactiv (0 = activ) */ Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactiv (0 = activ) */ Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
@@ -410,7 +410,7 @@ enum {
#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
/* RAM Interface Registers */ /* RAM Interface Registers */
/* B3_RI_CTRL 16 bit RAM Iface Control Register */ /* B3_RI_CTRL 16 bit RAM Interface Control Register */
enum { enum {
RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
@@ -613,7 +613,7 @@ enum {
BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segmen. error (Tx) */ BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
BMU_START = 1<<8, /* Start Rx/Tx Queue */ BMU_START = 1<<8, /* Start Rx/Tx Queue */
@@ -636,7 +636,7 @@ enum {
enum { enum {
BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segm. length mism. */ BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
}; };
/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/