Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits) MIPS: O32: Provide definition of registers ta0 .. ta3. MIPS: perf: Add Octeon support for hardware perf. MIPS: perf: Add support for 64-bit perf counters. MIPS: perf: Reorganize contents of perf support files. MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c MIPS: Add accessor macros for 64-bit performance counter registers. MIPS: Add probes for more Octeon II CPUs. MIPS: Add more CPU identifiers for Octeon II CPUs. MIPS: XLR, XLS: Add comment for smp setup MIPS: JZ4740: GPIO: Check correct IRQ in demux handler MIPS: JZ4740: GPIO: Simplify IRQ demuxer MIPS: JZ4740: Use generic irq chip MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines MIPS: Alchemy: kill au1xxx.h header MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep MIPS: Alchemy: Redo PCI as platform driver MIPS: Alchemy: more base address cleanup MIPS: Alchemy: rewrite USB platform setup. MIPS: Alchemy: abstract USB block control register access ... Fix up trivial conflicts in: arch/mips/alchemy/devboards/db1x00/platform.c drivers/ide/Kconfig drivers/mmc/host/au1xmmc.c drivers/video/Kconfig sound/mips/Kconfig
This commit is contained in:
Linus Torvalds
@ -114,4 +114,28 @@ unsigned long run_uncached(void *func);
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extern void *kmap_coherent(struct page *page, unsigned long addr);
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extern void kunmap_coherent(void);
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#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
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static inline void flush_kernel_dcache_page(struct page *page)
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{
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BUG_ON(cpu_has_dc_aliases && PageHighMem(page));
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}
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/*
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* For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
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* cache writeback and invalidate operation.
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*/
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extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
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static inline void flush_kernel_vmap_range(void *vaddr, int size)
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{
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if (cpu_has_dc_aliases)
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__flush_kernel_vmap_range((unsigned long) vaddr, size);
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}
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static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
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{
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if (cpu_has_dc_aliases)
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__flush_kernel_vmap_range((unsigned long) vaddr, size);
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}
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#endif /* _ASM_CACHEFLUSH_H */
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@ -135,6 +135,9 @@
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#define PRID_IMP_CAVIUM_CN50XX 0x0600
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#define PRID_IMP_CAVIUM_CN52XX 0x0700
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#define PRID_IMP_CAVIUM_CN63XX 0x9000
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#define PRID_IMP_CAVIUM_CN68XX 0x9100
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#define PRID_IMP_CAVIUM_CN66XX 0x9200
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#define PRID_IMP_CAVIUM_CN61XX 0x9300
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
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@ -329,14 +329,10 @@ static inline void pfx##write##bwlq(type val, \
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"dsrl32 %L0, %L0, 0" "\n\t" \
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"dsll32 %M0, %M0, 0" "\n\t" \
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"or %L0, %L0, %M0" "\n\t" \
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".set push" "\n\t" \
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".set noreorder" "\n\t" \
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".set nomacro" "\n\t" \
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"sd %L0, %2" "\n\t" \
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".set pop" "\n\t" \
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".set mips0" "\n" \
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: "=r" (__tmp) \
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: "0" (__val), "R" (*__mem)); \
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: "0" (__val), "m" (*__mem)); \
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if (irq) \
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local_irq_restore(__flags); \
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} else \
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@ -359,16 +355,12 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
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local_irq_save(__flags); \
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__asm__ __volatile__( \
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".set mips3" "\t\t# __readq" "\n\t" \
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".set push" "\n\t" \
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".set noreorder" "\n\t" \
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".set nomacro" "\n\t" \
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"ld %L0, %1" "\n\t" \
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".set pop" "\n\t" \
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"dsra32 %M0, %L0, 0" "\n\t" \
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"sll %L0, %L0, 0" "\n\t" \
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".set mips0" "\n" \
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: "=r" (__val) \
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: "R" (*__mem)); \
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: "m" (*__mem)); \
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if (irq) \
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local_irq_restore(__flags); \
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} else { \
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@ -245,6 +245,23 @@ void alchemy_sleep_au1000(void);
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void alchemy_sleep_au1550(void);
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void au_sleep(void);
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/* USB: drivers/usb/host/alchemy-common.c */
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enum alchemy_usb_block {
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ALCHEMY_USB_OHCI0,
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ALCHEMY_USB_UDC0,
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ALCHEMY_USB_EHCI0,
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ALCHEMY_USB_OTG0,
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};
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int alchemy_usb_control(int block, int enable);
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/* PCI controller platform data */
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struct alchemy_pci_platdata {
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int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
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int (*board_pci_idsel)(unsigned int devsel, int assert);
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/* bits to set/clear in PCI_CONFIG register */
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unsigned long pci_cfg_set;
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unsigned long pci_cfg_clr;
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};
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/* SOC Interrupt numbers */
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@ -575,38 +592,95 @@ enum soc_au1200_ints {
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#endif /* !defined (_LANGUAGE_ASSEMBLY) */
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/*
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* SDRAM register offsets
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* Physical base addresses for integrated peripherals
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* 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
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*/
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#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
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defined(CONFIG_SOC_AU1100)
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#define MEM_SDMODE0 0x0000
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#define MEM_SDMODE1 0x0004
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#define MEM_SDMODE2 0x0008
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#define MEM_SDADDR0 0x000C
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#define MEM_SDADDR1 0x0010
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#define MEM_SDADDR2 0x0014
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#define MEM_SDREFCFG 0x0018
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#define MEM_SDPRECMD 0x001C
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#define MEM_SDAUTOREF 0x0020
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#define MEM_SDWRMD0 0x0024
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#define MEM_SDWRMD1 0x0028
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#define MEM_SDWRMD2 0x002C
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#define MEM_SDSLEEP 0x0030
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#define MEM_SDSMCKE 0x0034
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/*
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* MEM_SDMODE register content definitions
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*/
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#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
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#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
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#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
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#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
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#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */
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#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
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#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
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#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
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#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
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#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */
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#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
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#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
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#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
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#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
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#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
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#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
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#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
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#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
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#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
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#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
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#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
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#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
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#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
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#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
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#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
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#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
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#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */
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#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
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#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
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#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
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#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
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#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
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#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
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#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
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#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
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#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
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#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */
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#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
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#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
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#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
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#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
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#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
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#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
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#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
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#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
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#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
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#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
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#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
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#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */
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#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
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#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
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#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
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#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
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#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */
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#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */
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#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */
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/* Au1000 SDRAM memory controller register offsets */
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#define AU1000_MEM_SDMODE0 0x0000
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#define AU1000_MEM_SDMODE1 0x0004
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#define AU1000_MEM_SDMODE2 0x0008
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#define AU1000_MEM_SDADDR0 0x000C
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#define AU1000_MEM_SDADDR1 0x0010
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#define AU1000_MEM_SDADDR2 0x0014
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#define AU1000_MEM_SDREFCFG 0x0018
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#define AU1000_MEM_SDPRECMD 0x001C
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#define AU1000_MEM_SDAUTOREF 0x0020
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#define AU1000_MEM_SDWRMD0 0x0024
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#define AU1000_MEM_SDWRMD1 0x0028
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#define AU1000_MEM_SDWRMD2 0x002C
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#define AU1000_MEM_SDSLEEP 0x0030
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#define AU1000_MEM_SDSMCKE 0x0034
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/* MEM_SDMODE register content definitions */
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#define MEM_SDMODE_F (1 << 22)
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#define MEM_SDMODE_SR (1 << 21)
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#define MEM_SDMODE_BS (1 << 20)
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#define MEM_SDMODE_RS (3 << 18)
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#define MEM_SDMODE_CS (7 << 15)
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#define MEM_SDMODE_TRAS (15 << 11)
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#define MEM_SDMODE_TMRD (3 << 9)
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#define MEM_SDMODE_TRAS (15 << 11)
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#define MEM_SDMODE_TMRD (3 << 9)
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#define MEM_SDMODE_TWR (3 << 7)
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#define MEM_SDMODE_TRP (3 << 5)
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#define MEM_SDMODE_TRCD (3 << 3)
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#define MEM_SDMODE_TRCD (3 << 3)
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#define MEM_SDMODE_TCL (7 << 0)
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#define MEM_SDMODE_BS_2Bank (0 << 20)
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@ -628,173 +702,43 @@ enum soc_au1200_ints {
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#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
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#define MEM_SDMODE_TCL_N(N) ((N) << 0)
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/*
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* MEM_SDADDR register contents definitions
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*/
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/* MEM_SDADDR register contents definitions */
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#define MEM_SDADDR_E (1 << 20)
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#define MEM_SDADDR_CSBA (0x03FF << 10)
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#define MEM_SDADDR_CSBA (0x03FF << 10)
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#define MEM_SDADDR_CSMASK (0x03FF << 0)
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#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
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#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
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/*
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* MEM_SDREFCFG register content definitions
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*/
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/* MEM_SDREFCFG register content definitions */
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#define MEM_SDREFCFG_TRC (15 << 28)
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#define MEM_SDREFCFG_TRPM (3 << 26)
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#define MEM_SDREFCFG_E (1 << 25)
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#define MEM_SDREFCFG_RE (0x1ffffff << 0)
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#define MEM_SDREFCFG_RE (0x1ffffff << 0)
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#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
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#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
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#define MEM_SDREFCFG_REF_N(N) (N)
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#endif
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/***********************************************************************/
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/*
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* Au1550 SDRAM Register Offsets
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*/
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/***********************************************************************/
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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#define MEM_SDMODE0 0x0800
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#define MEM_SDMODE1 0x0808
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#define MEM_SDMODE2 0x0810
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#define MEM_SDADDR0 0x0820
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#define MEM_SDADDR1 0x0828
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#define MEM_SDADDR2 0x0830
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#define MEM_SDCONFIGA 0x0840
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#define MEM_SDCONFIGB 0x0848
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#define MEM_SDSTAT 0x0850
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#define MEM_SDERRADDR 0x0858
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#define MEM_SDSTRIDE0 0x0860
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#define MEM_SDSTRIDE1 0x0868
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#define MEM_SDSTRIDE2 0x0870
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#define MEM_SDWRMD0 0x0880
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#define MEM_SDWRMD1 0x0888
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#define MEM_SDWRMD2 0x0890
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#define MEM_SDPRECMD 0x08C0
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#define MEM_SDAUTOREF 0x08C8
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#define MEM_SDSREF 0x08D0
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#define MEM_SDSLEEP MEM_SDSREF
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#endif
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/*
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* Physical base addresses for integrated peripherals
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* 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
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*/
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#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
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#define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */
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#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
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#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
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#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
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#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
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#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */
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#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
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#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
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#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
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#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
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#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
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#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
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#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
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#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
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#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
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#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
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#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
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#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */
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#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
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#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
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#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
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#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
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#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
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#ifdef CONFIG_SOC_AU1000
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#define MEM_PHYS_ADDR 0x14000000
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#define STATIC_MEM_PHYS_ADDR 0x14001000
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#define USBH_PHYS_ADDR 0x10100000
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#define IRDA_PHYS_ADDR 0x10300000
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#define SSI0_PHYS_ADDR 0x11600000
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#define SSI1_PHYS_ADDR 0x11680000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
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#endif
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/********************************************************************/
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#ifdef CONFIG_SOC_AU1500
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#define MEM_PHYS_ADDR 0x14000000
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#define STATIC_MEM_PHYS_ADDR 0x14001000
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#define USBH_PHYS_ADDR 0x10100000
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#define PCI_PHYS_ADDR 0x14005000
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#define PCI_MEM_PHYS_ADDR 0x400000000ULL
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#define PCI_IO_PHYS_ADDR 0x500000000ULL
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#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
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#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
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#endif
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/********************************************************************/
|
||||
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#ifdef CONFIG_SOC_AU1100
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#define MEM_PHYS_ADDR 0x14000000
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#define STATIC_MEM_PHYS_ADDR 0x14001000
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#define USBH_PHYS_ADDR 0x10100000
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#define IRDA_PHYS_ADDR 0x10300000
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#define SSI0_PHYS_ADDR 0x11600000
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#define SSI1_PHYS_ADDR 0x11680000
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#define LCD_PHYS_ADDR 0x15000000
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#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
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#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
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#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
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#endif
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||||
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||||
/***********************************************************************/
|
||||
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#ifdef CONFIG_SOC_AU1550
|
||||
#define MEM_PHYS_ADDR 0x14000000
|
||||
#define STATIC_MEM_PHYS_ADDR 0x14001000
|
||||
#define USBH_PHYS_ADDR 0x14020000
|
||||
#define PCI_PHYS_ADDR 0x14005000
|
||||
#define PE_PHYS_ADDR 0x14008000
|
||||
#define PSC0_PHYS_ADDR 0x11A00000
|
||||
#define PSC1_PHYS_ADDR 0x11B00000
|
||||
#define PSC2_PHYS_ADDR 0x10A00000
|
||||
#define PSC3_PHYS_ADDR 0x10B00000
|
||||
#define PCI_MEM_PHYS_ADDR 0x400000000ULL
|
||||
#define PCI_IO_PHYS_ADDR 0x500000000ULL
|
||||
#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
|
||||
#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
|
||||
#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
|
||||
#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
|
||||
#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
|
||||
#endif
|
||||
|
||||
/***********************************************************************/
|
||||
|
||||
#ifdef CONFIG_SOC_AU1200
|
||||
#define MEM_PHYS_ADDR 0x14000000
|
||||
#define STATIC_MEM_PHYS_ADDR 0x14001000
|
||||
#define AES_PHYS_ADDR 0x10300000
|
||||
#define CIM_PHYS_ADDR 0x14004000
|
||||
#define USBM_PHYS_ADDR 0x14020000
|
||||
#define USBH_PHYS_ADDR 0x14020100
|
||||
#define PSC0_PHYS_ADDR 0x11A00000
|
||||
#define PSC1_PHYS_ADDR 0x11B00000
|
||||
#define LCD_PHYS_ADDR 0x15000000
|
||||
#define SWCNT_PHYS_ADDR 0x1110010C
|
||||
#define MAEFE_PHYS_ADDR 0x14012000
|
||||
#define MAEBE_PHYS_ADDR 0x14010000
|
||||
#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
|
||||
#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
|
||||
#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
|
||||
#endif
|
||||
/* Au1550 SDRAM Register Offsets */
|
||||
#define AU1550_MEM_SDMODE0 0x0800
|
||||
#define AU1550_MEM_SDMODE1 0x0808
|
||||
#define AU1550_MEM_SDMODE2 0x0810
|
||||
#define AU1550_MEM_SDADDR0 0x0820
|
||||
#define AU1550_MEM_SDADDR1 0x0828
|
||||
#define AU1550_MEM_SDADDR2 0x0830
|
||||
#define AU1550_MEM_SDCONFIGA 0x0840
|
||||
#define AU1550_MEM_SDCONFIGB 0x0848
|
||||
#define AU1550_MEM_SDSTAT 0x0850
|
||||
#define AU1550_MEM_SDERRADDR 0x0858
|
||||
#define AU1550_MEM_SDSTRIDE0 0x0860
|
||||
#define AU1550_MEM_SDSTRIDE1 0x0868
|
||||
#define AU1550_MEM_SDSTRIDE2 0x0870
|
||||
#define AU1550_MEM_SDWRMD0 0x0880
|
||||
#define AU1550_MEM_SDWRMD1 0x0888
|
||||
#define AU1550_MEM_SDWRMD2 0x0890
|
||||
#define AU1550_MEM_SDPRECMD 0x08C0
|
||||
#define AU1550_MEM_SDAUTOREF 0x08C8
|
||||
#define AU1550_MEM_SDSREF 0x08D0
|
||||
#define AU1550_MEM_SDSLEEP MEM_SDSREF
|
||||
|
||||
/* Static Bus Controller */
|
||||
#define MEM_STCFG0 0xB4001000
|
||||
@ -813,81 +757,14 @@ enum soc_au1200_ints {
|
||||
#define MEM_STTIME3 0xB4001034
|
||||
#define MEM_STADDR3 0xB4001038
|
||||
|
||||
#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
|
||||
#define MEM_STNDCTL 0xB4001100
|
||||
#define MEM_STSTAT 0xB4001104
|
||||
|
||||
#define MEM_STNAND_CMD 0x0
|
||||
#define MEM_STNAND_ADDR 0x4
|
||||
#define MEM_STNAND_DATA 0x20
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/* Au1000 */
|
||||
#ifdef CONFIG_SOC_AU1000
|
||||
|
||||
#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
|
||||
#define USB_HOST_CONFIG 0xB017FFFC
|
||||
#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
|
||||
#endif /* CONFIG_SOC_AU1000 */
|
||||
|
||||
/* Au1500 */
|
||||
#ifdef CONFIG_SOC_AU1500
|
||||
|
||||
#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
|
||||
#define USB_HOST_CONFIG 0xB017fffc
|
||||
#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
|
||||
#endif /* CONFIG_SOC_AU1500 */
|
||||
|
||||
/* Au1100 */
|
||||
#ifdef CONFIG_SOC_AU1100
|
||||
|
||||
#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
|
||||
#define USB_HOST_CONFIG 0xB017FFFC
|
||||
#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
|
||||
#endif /* CONFIG_SOC_AU1100 */
|
||||
|
||||
#ifdef CONFIG_SOC_AU1550
|
||||
|
||||
#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
|
||||
#define USB_OHCI_LEN 0x00060000
|
||||
#define USB_HOST_CONFIG 0xB4027ffc
|
||||
#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
|
||||
#endif /* CONFIG_SOC_AU1550 */
|
||||
|
||||
|
||||
#ifdef CONFIG_SOC_AU1200
|
||||
|
||||
#define USB_UOC_BASE 0x14020020
|
||||
#define USB_UOC_LEN 0x20
|
||||
#define USB_OHCI_BASE 0x14020100
|
||||
#define USB_OHCI_LEN 0x100
|
||||
#define USB_EHCI_BASE 0x14020200
|
||||
#define USB_EHCI_LEN 0x100
|
||||
#define USB_UDC_BASE 0x14022000
|
||||
#define USB_UDC_LEN 0x2000
|
||||
#define USB_MSR_BASE 0xB4020000
|
||||
#define USB_MSR_MCFG 4
|
||||
#define USBMSRMCFG_OMEMEN 0
|
||||
#define USBMSRMCFG_OBMEN 1
|
||||
#define USBMSRMCFG_EMEMEN 2
|
||||
#define USBMSRMCFG_EBMEN 3
|
||||
#define USBMSRMCFG_DMEMEN 4
|
||||
#define USBMSRMCFG_DBMEN 5
|
||||
#define USBMSRMCFG_GMEMEN 6
|
||||
#define USBMSRMCFG_OHCCLKEN 16
|
||||
#define USBMSRMCFG_EHCCLKEN 17
|
||||
#define USBMSRMCFG_UDCCLKEN 18
|
||||
#define USBMSRMCFG_PHYPLLEN 19
|
||||
#define USBMSRMCFG_RDCOMB 30
|
||||
#define USBMSRMCFG_PFEN 31
|
||||
|
||||
#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
|
||||
|
||||
#endif /* CONFIG_SOC_AU1200 */
|
||||
|
||||
/* Programmable Counters 0 and 1 */
|
||||
#define SYS_BASE 0xB1900000
|
||||
#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
|
||||
@ -958,56 +835,6 @@ enum soc_au1200_ints {
|
||||
# define I2S_CONTROL_D (1 << 1)
|
||||
# define I2S_CONTROL_CE (1 << 0)
|
||||
|
||||
/* USB Host Controller */
|
||||
#ifndef USB_OHCI_LEN
|
||||
#define USB_OHCI_LEN 0x00100000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SOC_AU1200
|
||||
|
||||
/* USB Device Controller */
|
||||
#define USBD_EP0RD 0xB0200000
|
||||
#define USBD_EP0WR 0xB0200004
|
||||
#define USBD_EP2WR 0xB0200008
|
||||
#define USBD_EP3WR 0xB020000C
|
||||
#define USBD_EP4RD 0xB0200010
|
||||
#define USBD_EP5RD 0xB0200014
|
||||
#define USBD_INTEN 0xB0200018
|
||||
#define USBD_INTSTAT 0xB020001C
|
||||
# define USBDEV_INT_SOF (1 << 12)
|
||||
# define USBDEV_INT_HF_BIT 6
|
||||
# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
|
||||
# define USBDEV_INT_CMPLT_BIT 0
|
||||
# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
|
||||
#define USBD_CONFIG 0xB0200020
|
||||
#define USBD_EP0CS 0xB0200024
|
||||
#define USBD_EP2CS 0xB0200028
|
||||
#define USBD_EP3CS 0xB020002C
|
||||
#define USBD_EP4CS 0xB0200030
|
||||
#define USBD_EP5CS 0xB0200034
|
||||
# define USBDEV_CS_SU (1 << 14)
|
||||
# define USBDEV_CS_NAK (1 << 13)
|
||||
# define USBDEV_CS_ACK (1 << 12)
|
||||
# define USBDEV_CS_BUSY (1 << 11)
|
||||
# define USBDEV_CS_TSIZE_BIT 1
|
||||
# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
|
||||
# define USBDEV_CS_STALL (1 << 0)
|
||||
#define USBD_EP0RDSTAT 0xB0200040
|
||||
#define USBD_EP0WRSTAT 0xB0200044
|
||||
#define USBD_EP2WRSTAT 0xB0200048
|
||||
#define USBD_EP3WRSTAT 0xB020004C
|
||||
#define USBD_EP4RDSTAT 0xB0200050
|
||||
#define USBD_EP5RDSTAT 0xB0200054
|
||||
# define USBDEV_FSTAT_FLUSH (1 << 6)
|
||||
# define USBDEV_FSTAT_UF (1 << 5)
|
||||
# define USBDEV_FSTAT_OF (1 << 4)
|
||||
# define USBDEV_FSTAT_FCNT_BIT 0
|
||||
# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
|
||||
#define USBD_ENABLE 0xB0200058
|
||||
# define USBDEV_ENABLE (1 << 1)
|
||||
# define USBDEV_CE (1 << 0)
|
||||
|
||||
#endif /* !CONFIG_SOC_AU1200 */
|
||||
|
||||
/* Ethernet Controllers */
|
||||
|
||||
@ -1322,7 +1149,6 @@ enum soc_au1200_ints {
|
||||
# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
|
||||
|
||||
/* Au1200 only */
|
||||
#ifdef CONFIG_SOC_AU1200
|
||||
#define SYS_PINFUNC_DMA (1 << 31)
|
||||
#define SYS_PINFUNC_S0A (1 << 30)
|
||||
#define SYS_PINFUNC_S1A (1 << 29)
|
||||
@ -1350,7 +1176,6 @@ enum soc_au1200_ints {
|
||||
#define SYS_PINFUNC_P0B (1 << 4)
|
||||
#define SYS_PINFUNC_U0T (1 << 3)
|
||||
#define SYS_PINFUNC_S1B (1 << 2)
|
||||
#endif
|
||||
|
||||
/* Power Management */
|
||||
#define SYS_SCRATCH0 0xB1900018
|
||||
@ -1406,12 +1231,12 @@ enum soc_au1200_ints {
|
||||
# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
|
||||
# define SYS_CS_DI2 (1 << 16)
|
||||
# define SYS_CS_CI2 (1 << 15)
|
||||
#ifdef CONFIG_SOC_AU1100
|
||||
|
||||
# define SYS_CS_ML_BIT 7
|
||||
# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
|
||||
# define SYS_CS_DL (1 << 6)
|
||||
# define SYS_CS_CL (1 << 5)
|
||||
#else
|
||||
|
||||
# define SYS_CS_MUH_BIT 12
|
||||
# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
|
||||
# define SYS_CS_DUH (1 << 11)
|
||||
@ -1420,7 +1245,7 @@ enum soc_au1200_ints {
|
||||
# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
|
||||
# define SYS_CS_DUD (1 << 6)
|
||||
# define SYS_CS_CUD (1 << 5)
|
||||
#endif
|
||||
|
||||
# define SYS_CS_MIR_BIT 2
|
||||
# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
|
||||
# define SYS_CS_DIR (1 << 1)
|
||||
@ -1467,58 +1292,30 @@ enum soc_au1200_ints {
|
||||
# define AC97C_RS (1 << 1)
|
||||
# define AC97C_CE (1 << 0)
|
||||
|
||||
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
|
||||
/* Au1500 PCI Controller */
|
||||
#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
|
||||
#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
|
||||
#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
|
||||
# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
|
||||
(1 << 25) | (1 << 26) | (1 << 27))
|
||||
#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
|
||||
#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
|
||||
#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
|
||||
#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
|
||||
#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
|
||||
#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
|
||||
#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
|
||||
#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
|
||||
#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
|
||||
#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
|
||||
#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
|
||||
#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
|
||||
|
||||
#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
|
||||
|
||||
/*
|
||||
* All of our structures, like PCI resource, have 32-bit members.
|
||||
* Drivers are expected to do an ioremap on the PCI MEM resource, but it's
|
||||
* hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
|
||||
* to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
|
||||
* (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
|
||||
* addresses. For PCI I/O, it's simpler because we get to do the ioremap
|
||||
* ourselves and then adjust the device's resources.
|
||||
/* The PCI chip selects are outside the 32bit space, and since we can't
|
||||
* just program the 36bit addresses into BARs, we have to take a chunk
|
||||
* out of the 32bit space and reserve it for PCI. When these addresses
|
||||
* are ioremap()ed, they'll be fixed up to the real 36bit address before
|
||||
* being passed to the real ioremap function.
|
||||
*/
|
||||
#define Au1500_EXT_CFG 0x600000000ULL
|
||||
#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
|
||||
#define Au1500_PCI_IO_START 0x500000000ULL
|
||||
#define Au1500_PCI_IO_END 0x5000FFFFFULL
|
||||
#define Au1500_PCI_MEM_START 0x440000000ULL
|
||||
#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
|
||||
#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
|
||||
#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
|
||||
|
||||
#define PCI_IO_START 0x00001000
|
||||
#define PCI_IO_END 0x000FFFFF
|
||||
#define PCI_MEM_START 0x40000000
|
||||
#define PCI_MEM_END 0x4FFFFFFF
|
||||
/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
|
||||
* adjust the device's resources.
|
||||
*/
|
||||
#define ALCHEMY_PCI_IOWIN_START 0x00001000
|
||||
#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
|
||||
|
||||
#define PCI_FIRST_DEVFN (0 << 3)
|
||||
#define PCI_LAST_DEVFN (19 << 3)
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
|
||||
#define IOPORT_RESOURCE_END 0xffffffff
|
||||
#define IOMEM_RESOURCE_START 0x10000000
|
||||
#define IOMEM_RESOURCE_END 0xfffffffffULL
|
||||
|
||||
#else /* Au1000 and Au1100 and Au1200 */
|
||||
#else
|
||||
|
||||
/* Don't allow any legacy ports probing */
|
||||
#define IOPORT_RESOURCE_START 0x10000000
|
||||
@ -1526,13 +1323,77 @@ enum soc_au1200_ints {
|
||||
#define IOMEM_RESOURCE_START 0x10000000
|
||||
#define IOMEM_RESOURCE_END 0xfffffffffULL
|
||||
|
||||
#define PCI_IO_START 0
|
||||
#define PCI_IO_END 0
|
||||
#define PCI_MEM_START 0
|
||||
#define PCI_MEM_END 0
|
||||
#define PCI_FIRST_DEVFN 0
|
||||
#define PCI_LAST_DEVFN 0
|
||||
|
||||
#endif
|
||||
|
||||
/* PCI controller block register offsets */
|
||||
#define PCI_REG_CMEM 0x0000
|
||||
#define PCI_REG_CONFIG 0x0004
|
||||
#define PCI_REG_B2BMASK_CCH 0x0008
|
||||
#define PCI_REG_B2BBASE0_VID 0x000C
|
||||
#define PCI_REG_B2BBASE1_SID 0x0010
|
||||
#define PCI_REG_MWMASK_DEV 0x0014
|
||||
#define PCI_REG_MWBASE_REV_CCL 0x0018
|
||||
#define PCI_REG_ERR_ADDR 0x001C
|
||||
#define PCI_REG_SPEC_INTACK 0x0020
|
||||
#define PCI_REG_ID 0x0100
|
||||
#define PCI_REG_STATCMD 0x0104
|
||||
#define PCI_REG_CLASSREV 0x0108
|
||||
#define PCI_REG_PARAM 0x010C
|
||||
#define PCI_REG_MBAR 0x0110
|
||||
#define PCI_REG_TIMEOUT 0x0140
|
||||
|
||||
/* PCI controller block register bits */
|
||||
#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
|
||||
#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
|
||||
#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
|
||||
#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
|
||||
#define PCI_CONFIG_ET (1 << 26) /* error in target mode */
|
||||
#define PCI_CONFIG_EF (1 << 25) /* fatal error */
|
||||
#define PCI_CONFIG_EP (1 << 24) /* parity error */
|
||||
#define PCI_CONFIG_EM (1 << 23) /* multiple errors */
|
||||
#define PCI_CONFIG_BM (1 << 22) /* bad master error */
|
||||
#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
|
||||
#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
|
||||
#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
|
||||
#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
|
||||
#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
|
||||
#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
|
||||
#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
|
||||
#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
|
||||
#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
|
||||
#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
|
||||
#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
|
||||
#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
|
||||
#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
|
||||
#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
|
||||
#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
|
||||
#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
|
||||
#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
|
||||
#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
|
||||
#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
|
||||
#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
|
||||
#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
|
||||
#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
|
||||
#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
|
||||
#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
|
||||
#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
|
||||
#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
|
||||
#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
|
||||
#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
|
||||
#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
|
||||
#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
|
||||
#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
|
||||
#define PCI_ID_DID(x) (((x) & 0xffff) << 16)
|
||||
#define PCI_ID_VID(x) ((x) & 0xffff)
|
||||
#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
|
||||
#define PCI_STATCMD_CMD(x) ((x) & 0xffff)
|
||||
#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
|
||||
#define PCI_CLASSREV_REV(x) ((x) & 0xff)
|
||||
#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
|
||||
#define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
|
||||
#define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
|
||||
#define PCI_PARAM_CLS(x) ((x) & 0xff)
|
||||
#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
|
||||
#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,43 +0,0 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef _AU1XXX_H_
|
||||
#define _AU1XXX_H_
|
||||
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
|
||||
#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
|
||||
defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
|
||||
#include <asm/mach-db1x00/db1x00.h>
|
||||
|
||||
#elif defined(CONFIG_MIPS_PB1550)
|
||||
#include <asm/mach-pb1x00/pb1550.h>
|
||||
|
||||
#elif defined(CONFIG_MIPS_PB1200)
|
||||
#include <asm/mach-pb1x00/pb1200.h>
|
||||
|
||||
#elif defined(CONFIG_MIPS_DB1200)
|
||||
#include <asm/mach-db1x00/db1200.h>
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _AU1XXX_H_ */
|
||||
@ -126,66 +126,62 @@ typedef volatile struct au1xxx_ddma_desc {
|
||||
#define SW_STATUS_INUSE (1 << 0)
|
||||
|
||||
/* Command 0 device IDs. */
|
||||
#ifdef CONFIG_SOC_AU1550
|
||||
#define DSCR_CMD0_UART0_TX 0
|
||||
#define DSCR_CMD0_UART0_RX 1
|
||||
#define DSCR_CMD0_UART3_TX 2
|
||||
#define DSCR_CMD0_UART3_RX 3
|
||||
#define DSCR_CMD0_DMA_REQ0 4
|
||||
#define DSCR_CMD0_DMA_REQ1 5
|
||||
#define DSCR_CMD0_DMA_REQ2 6
|
||||
#define DSCR_CMD0_DMA_REQ3 7
|
||||
#define DSCR_CMD0_USBDEV_RX0 8
|
||||
#define DSCR_CMD0_USBDEV_TX0 9
|
||||
#define DSCR_CMD0_USBDEV_TX1 10
|
||||
#define DSCR_CMD0_USBDEV_TX2 11
|
||||
#define DSCR_CMD0_USBDEV_RX3 12
|
||||
#define DSCR_CMD0_USBDEV_RX4 13
|
||||
#define DSCR_CMD0_PSC0_TX 14
|
||||
#define DSCR_CMD0_PSC0_RX 15
|
||||
#define DSCR_CMD0_PSC1_TX 16
|
||||
#define DSCR_CMD0_PSC1_RX 17
|
||||
#define DSCR_CMD0_PSC2_TX 18
|
||||
#define DSCR_CMD0_PSC2_RX 19
|
||||
#define DSCR_CMD0_PSC3_TX 20
|
||||
#define DSCR_CMD0_PSC3_RX 21
|
||||
#define DSCR_CMD0_PCI_WRITE 22
|
||||
#define DSCR_CMD0_NAND_FLASH 23
|
||||
#define DSCR_CMD0_MAC0_RX 24
|
||||
#define DSCR_CMD0_MAC0_TX 25
|
||||
#define DSCR_CMD0_MAC1_RX 26
|
||||
#define DSCR_CMD0_MAC1_TX 27
|
||||
#endif /* CONFIG_SOC_AU1550 */
|
||||
#define AU1550_DSCR_CMD0_UART0_TX 0
|
||||
#define AU1550_DSCR_CMD0_UART0_RX 1
|
||||
#define AU1550_DSCR_CMD0_UART3_TX 2
|
||||
#define AU1550_DSCR_CMD0_UART3_RX 3
|
||||
#define AU1550_DSCR_CMD0_DMA_REQ0 4
|
||||
#define AU1550_DSCR_CMD0_DMA_REQ1 5
|
||||
#define AU1550_DSCR_CMD0_DMA_REQ2 6
|
||||
#define AU1550_DSCR_CMD0_DMA_REQ3 7
|
||||
#define AU1550_DSCR_CMD0_USBDEV_RX0 8
|
||||
#define AU1550_DSCR_CMD0_USBDEV_TX0 9
|
||||
#define AU1550_DSCR_CMD0_USBDEV_TX1 10
|
||||
#define AU1550_DSCR_CMD0_USBDEV_TX2 11
|
||||
#define AU1550_DSCR_CMD0_USBDEV_RX3 12
|
||||
#define AU1550_DSCR_CMD0_USBDEV_RX4 13
|
||||
#define AU1550_DSCR_CMD0_PSC0_TX 14
|
||||
#define AU1550_DSCR_CMD0_PSC0_RX 15
|
||||
#define AU1550_DSCR_CMD0_PSC1_TX 16
|
||||
#define AU1550_DSCR_CMD0_PSC1_RX 17
|
||||
#define AU1550_DSCR_CMD0_PSC2_TX 18
|
||||
#define AU1550_DSCR_CMD0_PSC2_RX 19
|
||||
#define AU1550_DSCR_CMD0_PSC3_TX 20
|
||||
#define AU1550_DSCR_CMD0_PSC3_RX 21
|
||||
#define AU1550_DSCR_CMD0_PCI_WRITE 22
|
||||
#define AU1550_DSCR_CMD0_NAND_FLASH 23
|
||||
#define AU1550_DSCR_CMD0_MAC0_RX 24
|
||||
#define AU1550_DSCR_CMD0_MAC0_TX 25
|
||||
#define AU1550_DSCR_CMD0_MAC1_RX 26
|
||||
#define AU1550_DSCR_CMD0_MAC1_TX 27
|
||||
|
||||
#ifdef CONFIG_SOC_AU1200
|
||||
#define DSCR_CMD0_UART0_TX 0
|
||||
#define DSCR_CMD0_UART0_RX 1
|
||||
#define DSCR_CMD0_UART1_TX 2
|
||||
#define DSCR_CMD0_UART1_RX 3
|
||||
#define DSCR_CMD0_DMA_REQ0 4
|
||||
#define DSCR_CMD0_DMA_REQ1 5
|
||||
#define DSCR_CMD0_MAE_BE 6
|
||||
#define DSCR_CMD0_MAE_FE 7
|
||||
#define DSCR_CMD0_SDMS_TX0 8
|
||||
#define DSCR_CMD0_SDMS_RX0 9
|
||||
#define DSCR_CMD0_SDMS_TX1 10
|
||||
#define DSCR_CMD0_SDMS_RX1 11
|
||||
#define DSCR_CMD0_AES_TX 13
|
||||
#define DSCR_CMD0_AES_RX 12
|
||||
#define DSCR_CMD0_PSC0_TX 14
|
||||
#define DSCR_CMD0_PSC0_RX 15
|
||||
#define DSCR_CMD0_PSC1_TX 16
|
||||
#define DSCR_CMD0_PSC1_RX 17
|
||||
#define DSCR_CMD0_CIM_RXA 18
|
||||
#define DSCR_CMD0_CIM_RXB 19
|
||||
#define DSCR_CMD0_CIM_RXC 20
|
||||
#define DSCR_CMD0_MAE_BOTH 21
|
||||
#define DSCR_CMD0_LCD 22
|
||||
#define DSCR_CMD0_NAND_FLASH 23
|
||||
#define DSCR_CMD0_PSC0_SYNC 24
|
||||
#define DSCR_CMD0_PSC1_SYNC 25
|
||||
#define DSCR_CMD0_CIM_SYNC 26
|
||||
#endif /* CONFIG_SOC_AU1200 */
|
||||
#define AU1200_DSCR_CMD0_UART0_TX 0
|
||||
#define AU1200_DSCR_CMD0_UART0_RX 1
|
||||
#define AU1200_DSCR_CMD0_UART1_TX 2
|
||||
#define AU1200_DSCR_CMD0_UART1_RX 3
|
||||
#define AU1200_DSCR_CMD0_DMA_REQ0 4
|
||||
#define AU1200_DSCR_CMD0_DMA_REQ1 5
|
||||
#define AU1200_DSCR_CMD0_MAE_BE 6
|
||||
#define AU1200_DSCR_CMD0_MAE_FE 7
|
||||
#define AU1200_DSCR_CMD0_SDMS_TX0 8
|
||||
#define AU1200_DSCR_CMD0_SDMS_RX0 9
|
||||
#define AU1200_DSCR_CMD0_SDMS_TX1 10
|
||||
#define AU1200_DSCR_CMD0_SDMS_RX1 11
|
||||
#define AU1200_DSCR_CMD0_AES_TX 13
|
||||
#define AU1200_DSCR_CMD0_AES_RX 12
|
||||
#define AU1200_DSCR_CMD0_PSC0_TX 14
|
||||
#define AU1200_DSCR_CMD0_PSC0_RX 15
|
||||
#define AU1200_DSCR_CMD0_PSC1_TX 16
|
||||
#define AU1200_DSCR_CMD0_PSC1_RX 17
|
||||
#define AU1200_DSCR_CMD0_CIM_RXA 18
|
||||
#define AU1200_DSCR_CMD0_CIM_RXB 19
|
||||
#define AU1200_DSCR_CMD0_CIM_RXC 20
|
||||
#define AU1200_DSCR_CMD0_MAE_BOTH 21
|
||||
#define AU1200_DSCR_CMD0_LCD 22
|
||||
#define AU1200_DSCR_CMD0_NAND_FLASH 23
|
||||
#define AU1200_DSCR_CMD0_PSC0_SYNC 24
|
||||
#define AU1200_DSCR_CMD0_PSC1_SYNC 25
|
||||
#define AU1200_DSCR_CMD0_CIM_SYNC 26
|
||||
|
||||
#define DSCR_CMD0_THROTTLE 30
|
||||
#define DSCR_CMD0_ALWAYS 31
|
||||
|
||||
@ -58,6 +58,7 @@ typedef struct {
|
||||
#endif
|
||||
int irq;
|
||||
u32 regbase;
|
||||
int ddma_id;
|
||||
} _auide_hwif;
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
@ -33,19 +33,6 @@
|
||||
#ifndef _AU1000_PSC_H_
|
||||
#define _AU1000_PSC_H_
|
||||
|
||||
/* The PSC base addresses. */
|
||||
#ifdef CONFIG_SOC_AU1550
|
||||
#define PSC0_BASE_ADDR 0xb1a00000
|
||||
#define PSC1_BASE_ADDR 0xb1b00000
|
||||
#define PSC2_BASE_ADDR 0xb0a00000
|
||||
#define PSC3_BASE_ADDR 0xb0b00000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AU1200
|
||||
#define PSC0_BASE_ADDR 0xb1a00000
|
||||
#define PSC1_BASE_ADDR 0xb1b00000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The PSC select and control registers are common to all protocols.
|
||||
*/
|
||||
@ -80,19 +67,6 @@
|
||||
#define PSC_AC97GPO_OFFSET 0x00000028
|
||||
#define PSC_AC97GPI_OFFSET 0x0000002c
|
||||
|
||||
#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
|
||||
#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
|
||||
#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
|
||||
#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
|
||||
#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
|
||||
#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
|
||||
#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
|
||||
#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
|
||||
#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
|
||||
#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
|
||||
#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
|
||||
#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
|
||||
|
||||
/* AC97 Config Register. */
|
||||
#define PSC_AC97CFG_RT_MASK (3 << 30)
|
||||
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
|
||||
|
||||
@ -347,17 +347,6 @@ static inline int alchemy_gpio2_to_irq(int gpio)
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
|
||||
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
|
||||
* register enables use of GPIOs as wake source.
|
||||
*/
|
||||
static inline void alchemy_gpio1_input_enable(void)
|
||||
{
|
||||
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
|
||||
__raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */
|
||||
wmb();
|
||||
}
|
||||
|
||||
/* GPIO2 shared interrupts and control */
|
||||
|
||||
static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
|
||||
@ -561,6 +550,7 @@ static inline int alchemy_irq_to_gpio(int irq)
|
||||
|
||||
#ifndef CONFIG_GPIOLIB
|
||||
|
||||
#ifdef CONFIG_ALCHEMY_GPIOINT_AU1000
|
||||
|
||||
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
|
||||
|
||||
@ -665,24 +655,7 @@ static inline void gpio_unexport(unsigned gpio)
|
||||
|
||||
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
||||
|
||||
|
||||
#else /* CONFIG GPIOLIB */
|
||||
|
||||
|
||||
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
|
||||
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
|
||||
|
||||
/* get everything through gpiolib */
|
||||
#define gpio_to_irq __gpio_to_irq
|
||||
#define gpio_get_value __gpio_get_value
|
||||
#define gpio_set_value __gpio_set_value
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
#define irq_to_gpio alchemy_irq_to_gpio
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
||||
|
||||
#endif /* CONFIG_ALCHEMY_GPIOINT_AU1000 */
|
||||
|
||||
#endif /* !CONFIG_GPIOLIB */
|
||||
|
||||
|
||||
@ -1,10 +1,83 @@
|
||||
/*
|
||||
* Alchemy GPIO support.
|
||||
*
|
||||
* With CONFIG_GPIOLIB=y different types of on-chip GPIO can be supported within
|
||||
* the same kernel image.
|
||||
* With CONFIG_GPIOLIB=n, your board must select ALCHEMY_GPIOINT_AU1XXX for the
|
||||
* appropriate CPU type (AU1000 currently).
|
||||
*/
|
||||
|
||||
#ifndef _ALCHEMY_GPIO_H_
|
||||
#define _ALCHEMY_GPIO_H_
|
||||
|
||||
#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000)
|
||||
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/gpio-au1000.h>
|
||||
|
||||
#endif
|
||||
/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
|
||||
* SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this
|
||||
* register enables use of GPIOs as wake source.
|
||||
*/
|
||||
static inline void alchemy_gpio1_input_enable(void)
|
||||
{
|
||||
void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
|
||||
__raw_writel(0, base + 0x110); /* the write op is key */
|
||||
wmb();
|
||||
}
|
||||
|
||||
|
||||
/* Linux gpio framework integration.
|
||||
*
|
||||
* 4 use cases of Alchemy GPIOS:
|
||||
*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
|
||||
* Board must register gpiochips.
|
||||
*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
|
||||
* A gpiochip for the 75 GPIOs is registered.
|
||||
*
|
||||
*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
|
||||
* the boards' gpio.h must provide the linux gpio wrapper functions,
|
||||
*
|
||||
*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
|
||||
* inlinable gpio functions are provided which enable access to the
|
||||
* Au1300 gpios only by using the numbers straight out of the data-
|
||||
* sheets.
|
||||
|
||||
* Cases 1 and 3 are intended for boards which want to provide their own
|
||||
* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
|
||||
* which are in part provided by spare Au1300 GPIO pins and in part by
|
||||
* an external FPGA but you still want them to be accssible in linux
|
||||
* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
|
||||
* as required).
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GPIOLIB
|
||||
|
||||
/* wraps the cpu-dependent irq_to_gpio functions */
|
||||
/* FIXME: gpiolib needs an irq_to_gpio hook */
|
||||
static inline int __au_irq_to_gpio(unsigned int irq)
|
||||
{
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
|
||||
return alchemy_irq_to_gpio(irq);
|
||||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
|
||||
#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
|
||||
|
||||
/* get everything through gpiolib */
|
||||
#define gpio_to_irq __gpio_to_irq
|
||||
#define gpio_get_value __gpio_get_value
|
||||
#define gpio_set_value __gpio_set_value
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
#define irq_to_gpio __au_irq_to_gpio
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
|
||||
|
||||
|
||||
#endif /* CONFIG_GPIOLIB */
|
||||
|
||||
#endif /* _ALCHEMY_GPIO_H_ */
|
||||
|
||||
@ -46,8 +46,6 @@
|
||||
|
||||
#define IDE_PHYS_ADDR 0x18800000
|
||||
#define IDE_REG_SHIFT 5
|
||||
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
|
||||
#define IDE_RQSIZE 128
|
||||
|
||||
#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
|
||||
#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
|
||||
|
||||
@ -31,15 +31,15 @@
|
||||
|
||||
#ifdef CONFIG_MIPS_DB1550
|
||||
|
||||
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
|
||||
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
|
||||
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
|
||||
#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
|
||||
#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
|
||||
#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
|
||||
|
||||
#define SPI_PSC_BASE PSC0_BASE_ADDR
|
||||
#define AC97_PSC_BASE PSC1_BASE_ADDR
|
||||
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
|
||||
#define I2S_PSC_BASE PSC3_BASE_ADDR
|
||||
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
|
||||
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
|
||||
#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
|
||||
#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
|
||||
|
||||
#define NAND_PHYS_ADDR 0x20000000
|
||||
|
||||
|
||||
@ -28,23 +28,23 @@
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/au1xxx_psc.h>
|
||||
|
||||
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
|
||||
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
|
||||
#define DBDMA_AC97_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_AC97_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
|
||||
#define DBDMA_I2S_TX_CHAN AU1200_DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_I2S_RX_CHAN AU1200_DSCR_CMD0_PSC1_RX
|
||||
|
||||
/*
|
||||
* SPI and SMB are muxed on the Pb1200 board.
|
||||
* Refer to board documentation.
|
||||
*/
|
||||
#define SPI_PSC_BASE PSC0_BASE_ADDR
|
||||
#define SMBUS_PSC_BASE PSC0_BASE_ADDR
|
||||
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
|
||||
#define SMBUS_PSC_BASE AU1550_PSC0_PHYS_ADDR
|
||||
/*
|
||||
* AC97 and I2S are muxed on the Pb1200 board.
|
||||
* Refer to board documentation.
|
||||
*/
|
||||
#define AC97_PSC_BASE PSC1_BASE_ADDR
|
||||
#define I2S_PSC_BASE PSC1_BASE_ADDR
|
||||
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
|
||||
#define I2S_PSC_BASE AU1550_PSC1_PHYS_ADDR
|
||||
|
||||
|
||||
#define BCSR_SYSTEM_VDDI 0x001F
|
||||
@ -76,8 +76,6 @@
|
||||
#define IDE_REG_SHIFT 5
|
||||
#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
|
||||
#define IDE_INT PB1200_IDE_INT
|
||||
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
|
||||
#define IDE_RQSIZE 128
|
||||
|
||||
#define NAND_PHYS_ADDR 0x1C000000
|
||||
|
||||
|
||||
@ -30,15 +30,15 @@
|
||||
#include <linux/types.h>
|
||||
#include <asm/mach-au1x00/au1xxx_psc.h>
|
||||
|
||||
#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
|
||||
#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
|
||||
#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
|
||||
#define DBDMA_AC97_TX_CHAN AU1550_DSCR_CMD0_PSC1_TX
|
||||
#define DBDMA_AC97_RX_CHAN AU1550_DSCR_CMD0_PSC1_RX
|
||||
#define DBDMA_I2S_TX_CHAN AU1550_DSCR_CMD0_PSC3_TX
|
||||
#define DBDMA_I2S_RX_CHAN AU1550_DSCR_CMD0_PSC3_RX
|
||||
|
||||
#define SPI_PSC_BASE PSC0_BASE_ADDR
|
||||
#define AC97_PSC_BASE PSC1_BASE_ADDR
|
||||
#define SMBUS_PSC_BASE PSC2_BASE_ADDR
|
||||
#define I2S_PSC_BASE PSC3_BASE_ADDR
|
||||
#define SPI_PSC_BASE AU1550_PSC0_PHYS_ADDR
|
||||
#define AC97_PSC_BASE AU1550_PSC1_PHYS_ADDR
|
||||
#define SMBUS_PSC_BASE AU1550_PSC2_PHYS_ADDR
|
||||
#define I2S_PSC_BASE AU1550_PSC3_PHYS_ADDR
|
||||
|
||||
/*
|
||||
* Timing values as described in databook, * ns value stripped of
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#ifndef __ASM_MIPS_PROM_H
|
||||
#define __ASM_MIPS_PROM_H
|
||||
#ifndef __ASM_MIPSPROM_H
|
||||
#define __ASM_MIPSPROM_H
|
||||
|
||||
#define PROM_RESET 0
|
||||
#define PROM_EXEC 1
|
||||
@ -73,4 +73,4 @@
|
||||
|
||||
extern char *prom_getenv(char *);
|
||||
|
||||
#endif /* __ASM_MIPS_PROM_H */
|
||||
#endif /* __ASM_MIPSPROM_H */
|
||||
|
||||
@ -1006,18 +1006,26 @@ do { \
|
||||
#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
|
||||
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
|
||||
#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
|
||||
#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
|
||||
#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
|
||||
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
|
||||
#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
|
||||
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
|
||||
#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
|
||||
#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
|
||||
#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
|
||||
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
|
||||
#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
|
||||
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
|
||||
#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
|
||||
#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
|
||||
#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
|
||||
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
|
||||
#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
|
||||
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
|
||||
#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
|
||||
#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
|
||||
#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
|
||||
|
||||
/* RM9000 PerfCount performance counter register */
|
||||
#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
|
||||
|
||||
@ -8,8 +8,8 @@
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#ifndef __ASM_MIPS_PROM_H
|
||||
#define __ASM_MIPS_PROM_H
|
||||
#ifndef __ASM_PROM_H
|
||||
#define __ASM_PROM_H
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
#include <asm/bootinfo.h>
|
||||
@ -25,4 +25,4 @@ extern void device_tree_init(void);
|
||||
static inline void device_tree_init(void) { }
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
#endif /* _ASM_MIPS_PROM_H */
|
||||
#endif /* __ASM_PROM_H */
|
||||
|
||||
@ -6,6 +6,8 @@
|
||||
* Copyright (C) 1985 MIPS Computer Systems, Inc.
|
||||
* Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
|
||||
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
|
||||
* Copyright (C) 2011 Wind River Systems,
|
||||
* written by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#ifndef _ASM_REGDEF_H
|
||||
#define _ASM_REGDEF_H
|
||||
@ -30,9 +32,13 @@
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define ta0 $12
|
||||
#define t5 $13
|
||||
#define ta1 $13
|
||||
#define t6 $14
|
||||
#define ta2 $14
|
||||
#define t7 $15
|
||||
#define ta3 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
|
||||
Reference in New Issue
Block a user