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[MIPS] MT: Reenable EIC support and add support for SOCit SC.

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Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Chris Dearman
2007-05-08 14:05:39 +01:00
committed by Ralf Baechle
parent ef300e4223
commit d725cf3818
5 changed files with 27 additions and 17 deletions
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10
arch/mips/kernel/irq-msc01.c
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@@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = {
};
void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
{
extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
_icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000);
_icctrl_msc = (unsigned long) ioremap (icubase, 0x40000);
/* Reset interrupt controller - initialises all registers to 0 */
MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
@@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
switch (imp->im_type) {
case MSC01_IRQ_EDGE:
set_irq_chip(base+n, &msc_edgeirq_type);
set_irq_chip(irqbase+n, &msc_edgeirq_type);
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
else
MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
break;
case MSC01_IRQ_LEVEL:
set_irq_chip(base+n, &msc_levelirq_type);
set_irq_chip(irqbase+n, &msc_levelirq_type);
if (cpu_has_veic)
MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
else
@@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
}
}
irq_base = base;
irq_base = irqbase;
MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */