x86: use native register access for native tlb flushing
currently these are paravirtulaized, doesn't appear any callers rely on this (no pv_ops backends are using native_tlb and overriding cr3/4 access). [ Impact: fix lockdep warning with paravirt and function tracer ] Signed-off-by: Chris Wright <chrisw@sous-sol.org> LKML-Reference: <20090423172138.GR3036@sequoia.sous-sol.org> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
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committed by
Steven Rostedt
parent
75db37d2f4
commit
d7285c6b5c
@@ -17,7 +17,7 @@
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static inline void __native_flush_tlb(void)
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static inline void __native_flush_tlb(void)
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{
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{
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write_cr3(read_cr3());
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native_write_cr3(native_read_cr3());
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}
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}
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static inline void __native_flush_tlb_global(void)
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static inline void __native_flush_tlb_global(void)
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@@ -32,11 +32,11 @@ static inline void __native_flush_tlb_global(void)
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*/
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*/
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raw_local_irq_save(flags);
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raw_local_irq_save(flags);
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cr4 = read_cr4();
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cr4 = native_read_cr4();
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/* clear PGE */
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/* clear PGE */
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write_cr4(cr4 & ~X86_CR4_PGE);
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native_write_cr4(cr4 & ~X86_CR4_PGE);
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/* write old PGE again and flush TLBs */
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/* write old PGE again and flush TLBs */
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write_cr4(cr4);
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native_write_cr4(cr4);
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raw_local_irq_restore(flags);
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raw_local_irq_restore(flags);
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}
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}
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