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drm/nv94-nvc0/disp: reorder writes to lane current control regs

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Fixes link training issues on some boards.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
2013-11-04 10:52:29 +10:00
parent 687d8f66b1
commit d7b023d87a
1 changed files with 8 additions and 4 deletions
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12
drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
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@@ -97,8 +97,9 @@ nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
{ {
struct nouveau_bios *bios = nouveau_bios(disp); struct nouveau_bios *bios = nouveau_bios(disp);
struct nv50_disp_priv *priv = (void *)disp; struct nv50_disp_priv *priv = (void *)disp;
const u32 shift = nv94_sor_dp_lane_map(priv, lane);
const u32 loff = nv94_sor_loff(outp); const u32 loff = nv94_sor_loff(outp);
u32 addr, shift = nv94_sor_dp_lane_map(priv, lane); u32 addr, data[3];
u8 ver, hdr, cnt, len; u8 ver, hdr, cnt, len;
struct nvbios_dpout info; struct nvbios_dpout info;
struct nvbios_dpcfg ocfg; struct nvbios_dpcfg ocfg;
@@ -113,9 +114,12 @@ nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
if (!addr) if (!addr)
return -EINVAL; return -EINVAL;
nv_mask(priv, 0x61c118 + loff, 0x000000ff << shift, ocfg.drv << shift); data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
nv_mask(priv, 0x61c120 + loff, 0x000000ff << shift, ocfg.pre << shift); data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
nv_mask(priv, 0x61c130 + loff, 0x0000ff00, ocfg.unk << 8); data[2] = nv_rd32(priv, 0x61c130 + loff) & ~(0x0000ff00);
nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.drv << shift));
nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pre << shift));
nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.unk << 8));
return 0; return 0;
} }