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KVM: SVM: sync V_TPR with LAPIC.TPR if CR8 write intercept is disabled

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If the CR8 write intercept is disabled the V_TPR field of the VMCB needs to be
synced with the TPR field in the local apic.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Avi Kivity <avi@qumranet.com>
This commit is contained in:
Joerg Roedel
2008-04-16 16:51:17 +02:00
committed by Avi Kivity
parent ec7cf6903f
commit d7bf8221a3
1 changed files with 12 additions and 0 deletions
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12
arch/x86/kvm/svm.c
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@@ -1620,6 +1620,16 @@ static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
{ {
} }
static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
{
struct vcpu_svm *svm = to_svm(vcpu);
if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
kvm_lapic_set_tpr(vcpu, cr8);
}
}
static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
{ {
struct vcpu_svm *svm = to_svm(vcpu); struct vcpu_svm *svm = to_svm(vcpu);
@@ -1791,6 +1801,8 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
stgi(); stgi();
sync_cr8_to_lapic(vcpu);
svm->next_rip = 0; svm->next_rip = 0;
} }