oprofile: Introduce op_x86_phys_to_virt()
This new function translates physical to virtual counter numbers. Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
@@ -27,12 +27,6 @@
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#include "op_counter.h"
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#include "op_counter.h"
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#include "op_x86_model.h"
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#include "op_x86_model.h"
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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DEFINE_PER_CPU(int, switch_index);
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#endif
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static struct op_x86_model_spec const *model;
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static struct op_x86_model_spec const *model;
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static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
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static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
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static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
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static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
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@@ -103,6 +97,21 @@ static void nmi_cpu_save_registers(struct op_msrs *msrs)
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}
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}
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}
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}
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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static DEFINE_PER_CPU(int, switch_index);
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inline int op_x86_phys_to_virt(int phys)
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{
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return __get_cpu_var(switch_index) + phys;
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}
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#else
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inline int op_x86_phys_to_virt(int phys) { return phys; }
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#endif
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static void free_msrs(void)
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static void free_msrs(void)
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{
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{
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int i;
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int i;
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@@ -248,31 +257,25 @@ static int nmi_setup(void)
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static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
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static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
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{
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{
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unsigned int si = __get_cpu_var(switch_index);
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struct op_msr *multiplex = msrs->multiplex;
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struct op_msr *multiplex = msrs->multiplex;
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unsigned int i;
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int i;
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for (i = 0; i < model->num_counters; ++i) {
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for (i = 0; i < model->num_counters; ++i) {
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int offset = i + si;
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int virt = op_x86_phys_to_virt(i);
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if (multiplex[offset].addr) {
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if (multiplex[virt].addr)
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rdmsrl(multiplex[offset].addr,
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rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
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multiplex[offset].saved);
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}
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}
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}
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}
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}
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static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
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static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
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{
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{
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unsigned int si = __get_cpu_var(switch_index);
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struct op_msr *multiplex = msrs->multiplex;
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struct op_msr *multiplex = msrs->multiplex;
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unsigned int i;
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int i;
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for (i = 0; i < model->num_counters; ++i) {
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for (i = 0; i < model->num_counters; ++i) {
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int offset = i + si;
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int virt = op_x86_phys_to_virt(i);
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if (multiplex[offset].addr) {
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if (multiplex[virt].addr)
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wrmsrl(multiplex[offset].addr,
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wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
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multiplex[offset].saved);
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}
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}
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}
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}
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}
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@@ -42,9 +42,6 @@
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#define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
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#define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
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static unsigned long reset_value[NUM_VIRT_COUNTERS];
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static unsigned long reset_value[NUM_VIRT_COUNTERS];
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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DECLARE_PER_CPU(int, switch_index);
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#endif
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#ifdef CONFIG_OPROFILE_IBS
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#ifdef CONFIG_OPROFILE_IBS
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@@ -141,23 +138,22 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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/* enable active counters */
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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for (i = 0; i < NUM_COUNTERS; ++i) {
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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int virt = op_x86_phys_to_virt(i);
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int offset = i + __get_cpu_var(switch_index);
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if (!counter_config[virt].enabled)
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#else
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continue;
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int offset = i;
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if (!msrs->counters[i].addr)
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#endif
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continue;
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if (counter_config[offset].enabled && msrs->counters[i].addr) {
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/* setup counter registers */
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/* setup counter registers */
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[offset]);
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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/* setup control registers */
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/* setup control registers */
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rdmsrl(msrs->controls[i].addr, val);
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[offset]);
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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}
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}
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}
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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@@ -170,16 +166,15 @@ static void op_amd_switch_ctrl(struct op_x86_model_spec const *model,
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/* enable active counters */
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/* enable active counters */
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for (i = 0; i < NUM_COUNTERS; ++i) {
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for (i = 0; i < NUM_COUNTERS; ++i) {
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int offset = i + __get_cpu_var(switch_index);
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int virt = op_x86_phys_to_virt(i);
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if (counter_config[offset].enabled) {
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if (!counter_config[virt].enabled)
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/* setup control registers */
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[offset]);
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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}
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}
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}
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#endif
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#endif
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@@ -292,19 +287,15 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
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int i;
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int i;
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for (i = 0; i < NUM_COUNTERS; ++i) {
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for (i = 0; i < NUM_COUNTERS; ++i) {
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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int virt = op_x86_phys_to_virt(i);
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int offset = i + __get_cpu_var(switch_index);
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if (!reset_value[virt])
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#else
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int offset = i;
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#endif
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if (!reset_value[offset])
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continue;
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continue;
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rdmsrl(msrs->counters[i].addr, val);
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rdmsrl(msrs->counters[i].addr, val);
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/* bit is clear if overflowed: */
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/* bit is clear if overflowed: */
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if (val & OP_CTR_OVERFLOW)
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if (val & OP_CTR_OVERFLOW)
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continue;
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continue;
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oprofile_add_sample(regs, offset);
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oprofile_add_sample(regs, virt);
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[offset]);
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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}
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}
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op_amd_handle_ibs(regs, msrs);
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op_amd_handle_ibs(regs, msrs);
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@@ -319,17 +310,12 @@ static void op_amd_start(struct op_msrs const * const msrs)
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int i;
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int i;
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for (i = 0; i < NUM_COUNTERS; ++i) {
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for (i = 0; i < NUM_COUNTERS; ++i) {
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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if (!reset_value[op_x86_phys_to_virt(i)])
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int offset = i + __get_cpu_var(switch_index);
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continue;
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#else
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int offset = i;
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#endif
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if (reset_value[offset]) {
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rdmsrl(msrs->controls[i].addr, val);
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rdmsrl(msrs->controls[i].addr, val);
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(msrs->controls[i].addr, val);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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}
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op_amd_start_ibs();
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op_amd_start_ibs();
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}
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}
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@@ -344,11 +330,7 @@ static void op_amd_stop(struct op_msrs const * const msrs)
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* pm callback
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* pm callback
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*/
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*/
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for (i = 0; i < NUM_COUNTERS; ++i) {
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for (i = 0; i < NUM_COUNTERS; ++i) {
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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if (!reset_value[op_x86_phys_to_virt(i)])
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if (!reset_value[i + per_cpu(switch_index, smp_processor_id())])
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#else
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if (!reset_value[i])
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#endif
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continue;
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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rdmsrl(msrs->controls[i].addr, val);
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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@@ -60,6 +60,7 @@ struct op_counter_config;
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extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
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extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
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struct op_counter_config *counter_config);
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struct op_counter_config *counter_config);
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extern int op_x86_phys_to_virt(int phys);
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extern struct op_x86_model_spec const op_ppro_spec;
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extern struct op_x86_model_spec const op_ppro_spec;
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extern struct op_x86_model_spec const op_p4_spec;
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extern struct op_x86_model_spec const op_p4_spec;
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