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[MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle
2007-10-11 23:45:58 +01:00
parent 61a33168be
commit d87d0c930a
1 changed files with 1 additions and 1 deletions
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arch/mips/kernel/smtc.c
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@@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
" addu %1, %0, 1 \n" " addu %1, %0, 1 \n"
" sc %1, %2 \n" " sc %1, %2 \n"
" beqz %1, 1b \n" " beqz %1, 1b \n"
" sync \n" __WEAK_LLSC_MB
: "=&r" (result), "=&r" (temp), "=m" (*pv) : "=&r" (result), "=&r" (temp), "=m" (*pv)
: "m" (*pv) : "m" (*pv)
: "memory"); : "memory");