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Merge branch 'for_3_2/omap_misc' of git://gitorious.org/omap-sw-develoment/linux-omap-dev into l3

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This commit is contained in:
Tony Lindgren
2011-09-28 14:53:59 -07:00
parent d93dc5c447 cefcadeaa7
commit dc9ca24f4d
5 changed files with 322 additions and 291 deletions
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130
arch/arm/mach-omap2/omap_l3_noc.c
View File

@@ -1,25 +1,25 @@
/* /*
* OMAP4XXX L3 Interconnect error handling driver * OMAP4XXX L3 Interconnect error handling driver
* *
* Copyright (C) 2011 Texas Corporation * Copyright (C) 2011 Texas Corporation
* Santosh Shilimkar <santosh.shilimkar@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com>
* Sricharan <r.sricharan@ti.com> * Sricharan <r.sricharan@ti.com>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version. * (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA * USA
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
@@ -55,12 +55,12 @@
static irqreturn_t l3_interrupt_handler(int irq, void *_l3) static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
{ {
struct omap4_l3 *l3 = _l3; struct omap4_l3 *l3 = _l3;
int inttype, i, j; int inttype, i, k;
int err_src = 0; int err_src = 0;
u32 std_err_main_addr, std_err_main, err_reg; u32 std_err_main, err_reg, clear, masterid;
u32 base, slave_addr, clear; void __iomem *base, *l3_targ_base;
char *source_name; char *target_name, *master_name = "UN IDENTIFIED";
/* Get the Type of interrupt */ /* Get the Type of interrupt */
inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
@@ -70,43 +70,50 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
* Read the regerr register of the clock domain * Read the regerr register of the clock domain
* to determine the source * to determine the source
*/ */
base = (u32)l3->l3_base[i]; base = l3->l3_base[i];
err_reg = readl(base + l3_flagmux[i] + (inttype << 3)); err_reg = __raw_readl(base + l3_flagmux[i] +
+ L3_FLAGMUX_REGERR0 + (inttype << 3));
/* Get the corresponding error and analyse */ /* Get the corresponding error and analyse */
if (err_reg) { if (err_reg) {
/* Identify the source from control status register */ /* Identify the source from control status register */
for (j = 0; !(err_reg & (1 << j)); j++) err_src = __ffs(err_reg);
;
err_src = j;
/* Read the stderrlog_main_source from clk domain */ /* Read the stderrlog_main_source from clk domain */
std_err_main_addr = base + *(l3_targ[i] + err_src); l3_targ_base = base + *(l3_targ[i] + err_src);
std_err_main = readl(std_err_main_addr); std_err_main = __raw_readl(l3_targ_base +
L3_TARG_STDERRLOG_MAIN);
masterid = __raw_readl(l3_targ_base +
L3_TARG_STDERRLOG_MSTADDR);
switch (std_err_main & CUSTOM_ERROR) { switch (std_err_main & CUSTOM_ERROR) {
case STANDARD_ERROR: case STANDARD_ERROR:
source_name = target_name =
l3_targ_stderrlog_main_name[i][err_src]; l3_targ_inst_name[i][err_src];
WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
slave_addr = std_err_main_addr + target_name,
L3_SLAVE_ADDRESS_OFFSET; __raw_readl(l3_targ_base +
WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", L3_TARG_STDERRLOG_SLVOFSLSB));
source_name, readl(slave_addr));
/* clear the std error log*/ /* clear the std error log*/
clear = std_err_main | CLEAR_STDERR_LOG; clear = std_err_main | CLEAR_STDERR_LOG;
writel(clear, std_err_main_addr); writel(clear, l3_targ_base +
L3_TARG_STDERRLOG_MAIN);
break; break;
case CUSTOM_ERROR: case CUSTOM_ERROR:
source_name = target_name =
l3_targ_stderrlog_main_name[i][err_src]; l3_targ_inst_name[i][err_src];
for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
WARN(true, "CUSTOM SRESP error with SOURCE:%s\n", if (masterid == l3_masters[k].id)
source_name); master_name =
l3_masters[k].name;
}
WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
master_name, target_name);
/* clear the std error log*/ /* clear the std error log*/
clear = std_err_main | CLEAR_STDERR_LOG; clear = std_err_main | CLEAR_STDERR_LOG;
writel(clear, std_err_main_addr); writel(clear, l3_targ_base +
L3_TARG_STDERRLOG_MAIN);
break; break;
default: default:
@@ -122,10 +129,9 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
static int __init omap4_l3_probe(struct platform_device *pdev) static int __init omap4_l3_probe(struct platform_device *pdev)
{ {
static struct omap4_l3 *l3; static struct omap4_l3 *l3;
struct resource *res; struct resource *res;
int ret; int ret;
int irq;
l3 = kzalloc(sizeof(*l3), GFP_KERNEL); l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
if (!l3) if (!l3)
@@ -177,27 +183,25 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
/* /*
* Setup interrupt Handlers * Setup interrupt Handlers
*/ */
irq = platform_get_irq(pdev, 0); l3->debug_irq = platform_get_irq(pdev, 0);
ret = request_irq(irq, ret = request_irq(l3->debug_irq,
l3_interrupt_handler, l3_interrupt_handler,
IRQF_DISABLED, "l3-dbg-irq", l3); IRQF_DISABLED, "l3-dbg-irq", l3);
if (ret) { if (ret) {
pr_crit("L3: request_irq failed to register for 0x%x\n", pr_crit("L3: request_irq failed to register for 0x%x\n",
OMAP44XX_IRQ_L3_DBG); OMAP44XX_IRQ_L3_DBG);
goto err3; goto err3;
} }
l3->debug_irq = irq;
irq = platform_get_irq(pdev, 1); l3->app_irq = platform_get_irq(pdev, 1);
ret = request_irq(irq, ret = request_irq(l3->app_irq,
l3_interrupt_handler, l3_interrupt_handler,
IRQF_DISABLED, "l3-app-irq", l3); IRQF_DISABLED, "l3-app-irq", l3);
if (ret) { if (ret) {
pr_crit("L3: request_irq failed to register for 0x%x\n", pr_crit("L3: request_irq failed to register for 0x%x\n",
OMAP44XX_IRQ_L3_APP); OMAP44XX_IRQ_L3_APP);
goto err4; goto err4;
} }
l3->app_irq = irq;
return 0; return 0;
@@ -216,7 +220,7 @@ err0:
static int __exit omap4_l3_remove(struct platform_device *pdev) static int __exit omap4_l3_remove(struct platform_device *pdev)
{ {
struct omap4_l3 *l3 = platform_get_drvdata(pdev); struct omap4_l3 *l3 = platform_get_drvdata(pdev);
free_irq(l3->app_irq, l3); free_irq(l3->app_irq, l3);
free_irq(l3->debug_irq, l3); free_irq(l3->debug_irq, l3);
@@ -229,9 +233,9 @@ static int __exit omap4_l3_remove(struct platform_device *pdev)
} }
static struct platform_driver omap4_l3_driver = { static struct platform_driver omap4_l3_driver = {
.remove = __exit_p(omap4_l3_remove), .remove = __exit_p(omap4_l3_remove),
.driver = { .driver = {
.name = "omap_l3_noc", .name = "omap_l3_noc",
}, },
}; };

224
arch/arm/mach-omap2/omap_l3_noc.h
View File

@@ -1,132 +1,162 @@
/* /*
* OMAP4XXX L3 Interconnect error handling driver header * OMAP4XXX L3 Interconnect error handling driver header
* *
* Copyright (C) 2011 Texas Corporation * Copyright (C) 2011 Texas Corporation
* Santosh Shilimkar <santosh.shilimkar@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com>
* sricharan <r.sricharan@ti.com> * sricharan <r.sricharan@ti.com>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version. * (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA * USA
*/ */
#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
/*
* L3 register offsets
*/
#define L3_MODULES 3 #define L3_MODULES 3
#define CLEAR_STDERR_LOG (1 << 31) #define CLEAR_STDERR_LOG (1 << 31)
#define CUSTOM_ERROR 0x2 #define CUSTOM_ERROR 0x2
#define STANDARD_ERROR 0x0 #define STANDARD_ERROR 0x0
#define INBAND_ERROR 0x0 #define INBAND_ERROR 0x0
#define EMIF_KERRLOG_OFFSET 0x10
#define L3_SLAVE_ADDRESS_OFFSET 0x14
#define LOGICAL_ADDR_ERRORLOG 0x4
#define L3_APPLICATION_ERROR 0x0 #define L3_APPLICATION_ERROR 0x0
#define L3_DEBUG_ERROR 0x1 #define L3_DEBUG_ERROR 0x1
u32 l3_flagmux[L3_MODULES] = { /* L3 TARG register offsets */
0x50C, #define L3_TARG_STDERRLOG_MAIN 0x48
0x100C, #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
0X020C #define L3_TARG_STDERRLOG_MSTADDR 0x68
#define L3_FLAGMUX_REGERR0 0xc
#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
static u32 l3_flagmux[L3_MODULES] = {
0x500,
0x1000,
0X0200
}; };
/* /* L3 Target standard Error register offsets */
* L3 Target standard Error register offsets static u32 l3_targ_inst_clk1[] = {
*/ 0x100, /* DMM1 */
u32 l3_targ_stderrlog_main_clk1[] = { 0x200, /* DMM2 */
0x148, /* DMM1 */ 0x300, /* ABE */
0x248, /* DMM2 */ 0x400, /* L4CFG */
0x348, /* ABE */ 0x600 /* CLK2 PWR DISC */
0x448, /* L4CFG */
0x648 /* CLK2 PWR DISC */
}; };
u32 l3_targ_stderrlog_main_clk2[] = { static u32 l3_targ_inst_clk2[] = {
0x548, /* CORTEX M3 */ 0x500, /* CORTEX M3 */
0x348, /* DSS */ 0x300, /* DSS */
0x148, /* GPMC */ 0x100, /* GPMC */
0x448, /* ISS */ 0x400, /* ISS */
0x748, /* IVAHD */ 0x700, /* IVAHD */
0xD48, /* missing in TRM corresponds to AES1*/ 0xD00, /* missing in TRM corresponds to AES1*/
0x948, /* L4 PER0*/ 0x900, /* L4 PER0*/
0x248, /* OCMRAM */ 0x200, /* OCMRAM */
0x148, /* missing in TRM corresponds to GPMC sERROR*/ 0x100, /* missing in TRM corresponds to GPMC sERROR*/
0x648, /* SGX */ 0x600, /* SGX */
0x848, /* SL2 */ 0x800, /* SL2 */
0x1648, /* C2C */ 0x1600, /* C2C */
0x1148, /* missing in TRM corresponds PWR DISC CLK1*/ 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
0xF48, /* missing in TRM corrsponds to SHA1*/ 0xF00, /* missing in TRM corrsponds to SHA1*/
0xE48, /* missing in TRM corresponds to AES2*/ 0xE00, /* missing in TRM corresponds to AES2*/
0xC48, /* L4 PER3 */ 0xC00, /* L4 PER3 */
0xA48, /* L4 PER1*/ 0xA00, /* L4 PER1*/
0xB48 /* L4 PER2*/ 0xB00 /* L4 PER2*/
}; };
u32 l3_targ_stderrlog_main_clk3[] = { static u32 l3_targ_inst_clk3[] = {
0x0148 /* EMUSS */ 0x0100 /* EMUSS */
}; };
char *l3_targ_stderrlog_main_name[L3_MODULES][18] = { static struct l3_masters_data {
u32 id;
char name[10];
} l3_masters[] = {
{ 0x0 , "MPU"},
{ 0x10, "CS_ADP"},
{ 0x14, "xxx"},
{ 0x20, "DSP"},
{ 0x30, "IVAHD"},
{ 0x40, "ISS"},
{ 0x44, "DucatiM3"},
{ 0x48, "FaceDetect"},
{ 0x50, "SDMA_Rd"},
{ 0x54, "SDMA_Wr"},
{ 0x58, "xxx"},
{ 0x5C, "xxx"},
{ 0x60, "SGX"},
{ 0x70, "DSS"},
{ 0x80, "C2C"},
{ 0x88, "xxx"},
{ 0x8C, "xxx"},
{ 0x90, "HSI"},
{ 0xA0, "MMC1"},
{ 0xA4, "MMC2"},
{ 0xA8, "MMC6"},
{ 0xB0, "UNIPRO1"},
{ 0xC0, "USBHOSTHS"},
{ 0xC4, "USBOTGHS"},
{ 0xC8, "USBHOSTFS"}
};
static char *l3_targ_inst_name[L3_MODULES][18] = {
{ {
"DMM1", "DMM1",
"DMM2", "DMM2",
"ABE", "ABE",
"L4CFG", "L4CFG",
"CLK2 PWR DISC", "CLK2 PWR DISC",
}, },
{ {
"CORTEX M3" , "CORTEX M3" ,
"DSS ", "DSS ",
"GPMC ", "GPMC ",
"ISS ", "ISS ",
"IVAHD ", "IVAHD ",
"AES1", "AES1",
"L4 PER0", "L4 PER0",
"OCMRAM ", "OCMRAM ",
"GPMC sERROR", "GPMC sERROR",
"SGX ", "SGX ",
"SL2 ", "SL2 ",
"C2C ", "C2C ",
"PWR DISC CLK1", "PWR DISC CLK1",
"SHA1", "SHA1",
"AES2", "AES2",
"L4 PER3", "L4 PER3",
"L4 PER1", "L4 PER1",
"L4 PER2", "L4 PER2",
}, },
{ {
"EMUSS", "EMUSS",
}, },
}; };
u32 *l3_targ[L3_MODULES] = { static u32 *l3_targ[L3_MODULES] = {
l3_targ_stderrlog_main_clk1, l3_targ_inst_clk1,
l3_targ_stderrlog_main_clk2, l3_targ_inst_clk2,
l3_targ_stderrlog_main_clk3, l3_targ_inst_clk3,
}; };
struct omap4_l3 { struct omap4_l3 {
struct device *dev; struct device *dev;
struct clk *ick; struct clk *ick;
/* memory base */ /* memory base */
void __iomem *l3_base[4]; void __iomem *l3_base[L3_MODULES];
int debug_irq; int debug_irq;
int app_irq; int app_irq;
}; };
#endif #endif

91
arch/arm/mach-omap2/omap_l3_smx.c
View File

@@ -1,26 +1,26 @@
/* /*
* OMAP3XXX L3 Interconnect Driver * OMAP3XXX L3 Interconnect Driver
* *
* Copyright (C) 2011 Texas Corporation * Copyright (C) 2011 Texas Corporation
* Felipe Balbi <balbi@ti.com> * Felipe Balbi <balbi@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com>
* Sricharan <r.sricharan@ti.com> * Sricharan <r.sricharan@ti.com>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version. * (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA * USA
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/slab.h> #include <linux/slab.h>
@@ -135,7 +135,7 @@ static char *omap3_l3_initiator_string(u8 initid)
} }
} }
/** /*
* omap3_l3_block_irq - handles a register block's irq * omap3_l3_block_irq - handles a register block's irq
* @l3: struct omap3_l3 * * @l3: struct omap3_l3 *
* @base: register block base address * @base: register block base address
@@ -150,30 +150,29 @@ static char *omap3_l3_initiator_string(u8 initid)
static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
u64 error, int error_addr) u64 error, int error_addr)
{ {
u8 code = omap3_l3_decode_error_code(error); u8 code = omap3_l3_decode_error_code(error);
u8 initid = omap3_l3_decode_initid(error); u8 initid = omap3_l3_decode_initid(error);
u8 multi = error & L3_ERROR_LOG_MULTI; u8 multi = error & L3_ERROR_LOG_MULTI;
u32 address = omap3_l3_decode_addr(error_addr); u32 address = omap3_l3_decode_addr(error_addr);
WARN(true, "%s seen by %s %s at address %x\n", WARN(true, "%s seen by %s %s at address %x\n",
omap3_l3_code_string(code), omap3_l3_code_string(code),
omap3_l3_initiator_string(initid), omap3_l3_initiator_string(initid),
multi ? "Multiple Errors" : "", multi ? "Multiple Errors" : "", address);
address);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
{ {
struct omap3_l3 *l3 = _l3; struct omap3_l3 *l3 = _l3;
u64 status, clear; u64 status, clear;
u64 error; u64 error;
u64 error_addr; u64 error_addr;
u64 err_source = 0; u64 err_source = 0;
void __iomem *base; void __iomem *base;
int int_type; int int_type;
irqreturn_t ret = IRQ_NONE; irqreturn_t ret = IRQ_NONE;
int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
if (!int_type) { if (!int_type) {
@@ -191,14 +190,12 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
} }
/* identify the error source */ /* identify the error source */
for (err_source = 0; !(status & (1 << err_source)); err_source++) err_source = __ffs(status);
;
base = l3->rt + *(omap3_l3_bases[int_type] + err_source); base = l3->rt + omap3_l3_bases[int_type][err_source];
error = omap3_l3_readll(base, L3_ERROR_LOG); error = omap3_l3_readll(base, L3_ERROR_LOG);
if (error) { if (error) {
error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
ret |= omap3_l3_block_irq(l3, error, error_addr); ret |= omap3_l3_block_irq(l3, error, error_addr);
} }
@@ -215,9 +212,9 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
static int __init omap3_l3_probe(struct platform_device *pdev) static int __init omap3_l3_probe(struct platform_device *pdev)
{ {
struct omap3_l3 *l3; struct omap3_l3 *l3;
struct resource *res; struct resource *res;
int ret; int ret;
l3 = kzalloc(sizeof(*l3), GFP_KERNEL); l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
if (!l3) if (!l3)

164
arch/arm/mach-omap2/omap_l3_smx.h
View File

@@ -1,26 +1,26 @@
/* /*
* OMAP3XXX L3 Interconnect Driver header * OMAP3XXX L3 Interconnect Driver header
* *
* Copyright (C) 2011 Texas Corporation * Copyright (C) 2011 Texas Corporation
* Felipe Balbi <balbi@ti.com> * Felipe Balbi <balbi@ti.com>
* Santosh Shilimkar <santosh.shilimkar@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com>
* sricharan <r.sricharan@ti.com> * sricharan <r.sricharan@ti.com>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version. * (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA * USA
*/ */
#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
@@ -40,7 +40,7 @@
#define L3_SI_CONTROL 0x020 #define L3_SI_CONTROL 0x020
#define L3_SI_FLAG_STATUS_0 0x510 #define L3_SI_FLAG_STATUS_0 0x510
const u64 shift = 1; static const u64 shift = 1;
#define L3_STATUS_0_MPUIA_BRST (shift << 0) #define L3_STATUS_0_MPUIA_BRST (shift << 0)
#define L3_STATUS_0_MPUIA_RSP (shift << 1) #define L3_STATUS_0_MPUIA_RSP (shift << 1)
@@ -78,32 +78,32 @@ const u64 shift = 1;
#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) #define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) #define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ #define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
| L3_STATUS_0_MPUIA_RSP \ | L3_STATUS_0_MPUIA_RSP \
| L3_STATUS_0_IVAIA_BRST \ | L3_STATUS_0_IVAIA_BRST \
| L3_STATUS_0_IVAIA_RSP \ | L3_STATUS_0_IVAIA_RSP \
| L3_STATUS_0_SGXIA_BRST \ | L3_STATUS_0_SGXIA_BRST \
| L3_STATUS_0_SGXIA_RSP \ | L3_STATUS_0_SGXIA_RSP \
| L3_STATUS_0_CAMIA_BRST \ | L3_STATUS_0_CAMIA_BRST \
| L3_STATUS_0_CAMIA_RSP \ | L3_STATUS_0_CAMIA_RSP \
| L3_STATUS_0_DISPIA_BRST \ | L3_STATUS_0_DISPIA_BRST \
| L3_STATUS_0_DISPIA_RSP \ | L3_STATUS_0_DISPIA_RSP \
| L3_STATUS_0_DMARDIA_BRST \ | L3_STATUS_0_DMARDIA_BRST \
| L3_STATUS_0_DMARDIA_RSP \ | L3_STATUS_0_DMARDIA_RSP \
| L3_STATUS_0_DMAWRIA_BRST \ | L3_STATUS_0_DMAWRIA_BRST \
| L3_STATUS_0_DMAWRIA_RSP \ | L3_STATUS_0_DMAWRIA_RSP \
| L3_STATUS_0_USBOTGIA_BRST \ | L3_STATUS_0_USBOTGIA_BRST \
| L3_STATUS_0_USBOTGIA_RSP \ | L3_STATUS_0_USBOTGIA_RSP \
| L3_STATUS_0_USBHOSTIA_BRST \ | L3_STATUS_0_USBHOSTIA_BRST \
| L3_STATUS_0_SMSTA_REQ \ | L3_STATUS_0_SMSTA_REQ \
| L3_STATUS_0_GPMCTA_REQ \ | L3_STATUS_0_GPMCTA_REQ \
| L3_STATUS_0_OCMRAMTA_REQ \ | L3_STATUS_0_OCMRAMTA_REQ \
| L3_STATUS_0_OCMROMTA_REQ \ | L3_STATUS_0_OCMROMTA_REQ \
| L3_STATUS_0_IVATA_REQ \ | L3_STATUS_0_IVATA_REQ \
| L3_STATUS_0_SGXTA_REQ \ | L3_STATUS_0_SGXTA_REQ \
| L3_STATUS_0_L4CORETA_REQ \ | L3_STATUS_0_L4CORETA_REQ \
| L3_STATUS_0_L4PERTA_REQ \ | L3_STATUS_0_L4PERTA_REQ \
| L3_STATUS_0_L4EMUTA_REQ \ | L3_STATUS_0_L4EMUTA_REQ \
| L3_STATUS_0_MAD2DTA_REQ) | L3_STATUS_0_MAD2DTA_REQ)
#define L3_SI_FLAG_STATUS_1 0x530 #define L3_SI_FLAG_STATUS_1 0x530
@@ -137,19 +137,19 @@ const u64 shift = 1;
enum omap3_l3_initiator_id { enum omap3_l3_initiator_id {
/* LCD has 1 ID */ /* LCD has 1 ID */
OMAP_L3_LCD = 29, OMAP_L3_LCD = 29,
/* SAD2D has 1 ID */ /* SAD2D has 1 ID */
OMAP_L3_SAD2D = 28, OMAP_L3_SAD2D = 28,
/* MPU has 5 IDs */ /* MPU has 5 IDs */
OMAP_L3_IA_MPU_SS_1 = 27, OMAP_L3_IA_MPU_SS_1 = 27,
OMAP_L3_IA_MPU_SS_2 = 26, OMAP_L3_IA_MPU_SS_2 = 26,
OMAP_L3_IA_MPU_SS_3 = 25, OMAP_L3_IA_MPU_SS_3 = 25,
OMAP_L3_IA_MPU_SS_4 = 24, OMAP_L3_IA_MPU_SS_4 = 24,
OMAP_L3_IA_MPU_SS_5 = 23, OMAP_L3_IA_MPU_SS_5 = 23,
/* IVA2.2 SS has 3 IDs*/ /* IVA2.2 SS has 3 IDs*/
OMAP_L3_IA_IVA_SS_1 = 22, OMAP_L3_IA_IVA_SS_1 = 22,
OMAP_L3_IA_IVA_SS_2 = 21, OMAP_L3_IA_IVA_SS_2 = 21,
OMAP_L3_IA_IVA_SS_3 = 20, OMAP_L3_IA_IVA_SS_3 = 20,
/* IVA 2.2 SS DMA has 6 IDS */ /* IVA 2.2 SS DMA has 6 IDS */
OMAP_L3_IA_IVA_SS_DMA_1 = 19, OMAP_L3_IA_IVA_SS_DMA_1 = 19,
OMAP_L3_IA_IVA_SS_DMA_2 = 18, OMAP_L3_IA_IVA_SS_DMA_2 = 18,
@@ -158,25 +158,25 @@ enum omap3_l3_initiator_id {
OMAP_L3_IA_IVA_SS_DMA_5 = 15, OMAP_L3_IA_IVA_SS_DMA_5 = 15,
OMAP_L3_IA_IVA_SS_DMA_6 = 14, OMAP_L3_IA_IVA_SS_DMA_6 = 14,
/* SGX has 1 ID */ /* SGX has 1 ID */
OMAP_L3_IA_SGX = 13, OMAP_L3_IA_SGX = 13,
/* CAM has 3 ID */ /* CAM has 3 ID */
OMAP_L3_IA_CAM_1 = 12, OMAP_L3_IA_CAM_1 = 12,
OMAP_L3_IA_CAM_2 = 11, OMAP_L3_IA_CAM_2 = 11,
OMAP_L3_IA_CAM_3 = 10, OMAP_L3_IA_CAM_3 = 10,
/* DAP has 1 ID */ /* DAP has 1 ID */
OMAP_L3_IA_DAP = 9, OMAP_L3_IA_DAP = 9,
/* SDMA WR has 2 IDs */ /* SDMA WR has 2 IDs */
OMAP_L3_SDMA_WR_1 = 8, OMAP_L3_SDMA_WR_1 = 8,
OMAP_L3_SDMA_WR_2 = 7, OMAP_L3_SDMA_WR_2 = 7,
/* SDMA RD has 4 IDs */ /* SDMA RD has 4 IDs */
OMAP_L3_SDMA_RD_1 = 6, OMAP_L3_SDMA_RD_1 = 6,
OMAP_L3_SDMA_RD_2 = 5, OMAP_L3_SDMA_RD_2 = 5,
OMAP_L3_SDMA_RD_3 = 4, OMAP_L3_SDMA_RD_3 = 4,
OMAP_L3_SDMA_RD_4 = 3, OMAP_L3_SDMA_RD_4 = 3,
/* HSUSB OTG has 1 ID */ /* HSUSB OTG has 1 ID */
OMAP_L3_USBOTG = 2, OMAP_L3_USBOTG = 2,
/* HSUSB HOST has 1 ID */ /* HSUSB HOST has 1 ID */
OMAP_L3_USBHOST = 1, OMAP_L3_USBHOST = 1,
}; };
enum omap3_l3_code { enum omap3_l3_code {
@@ -192,21 +192,21 @@ enum omap3_l3_code {
}; };
struct omap3_l3 { struct omap3_l3 {
struct device *dev; struct device *dev;
struct clk *ick; struct clk *ick;
/* memory base*/ /* memory base*/
void __iomem *rt; void __iomem *rt;
int debug_irq; int debug_irq;
int app_irq; int app_irq;
/* true when and inband functional error occurs */ /* true when and inband functional error occurs */
unsigned inband:1; unsigned inband:1;
}; };
/* offsets for l3 agents in order with the Flag status register */ /* offsets for l3 agents in order with the Flag status register */
unsigned int __iomem omap3_l3_app_bases[] = { static unsigned int omap3_l3_app_bases[] = {
/* MPU IA */ /* MPU IA */
0x1400, 0x1400,
0x1400, 0x1400,
@@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = {
0, 0,
}; };
unsigned int __iomem omap3_l3_debug_bases[] = { static unsigned int omap3_l3_debug_bases[] = {
/* MPU DATA IA */ /* MPU DATA IA */
0x1400, 0x1400,
/* RESERVED */ /* RESERVED */
@@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = {
/* REST RESERVED */ /* REST RESERVED */
}; };
u32 *omap3_l3_bases[] = { static u32 *omap3_l3_bases[] = {
omap3_l3_app_bases, omap3_l3_app_bases,
omap3_l3_debug_bases, omap3_l3_debug_bases,
}; };

4
arch/arm/plat-omap/include/plat/io.h
View File

@@ -228,13 +228,13 @@
#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE #define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
/* 0x4d000000 --> 0xfd200000 */ /* 0x4d000000 --> 0xfd200000 */
#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
#define OMAP44XX_EMIF2_SIZE SZ_1M #define OMAP44XX_EMIF2_SIZE SZ_1M
#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE #define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
/* 0x4e000000 --> 0xfd300000 */ /* 0x4e000000 --> 0xfd300000 */
#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
#define OMAP44XX_DMM_SIZE SZ_1M #define OMAP44XX_DMM_SIZE SZ_1M
#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
/* /*
* ---------------------------------------------------------------------------- * ----------------------------------------------------------------------------
* Omap specific register access * Omap specific register access