x86, perf: Clean up perf_event cpu code
The CPU support for perf events on x86 was implemented via included C files with #ifdefs. Clean this up by creating a new header file and compiling the vendor-specific files as needed. Signed-off-by: Kevin Winchester <kjwinchester@gmail.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1314747665-2090-1-git-send-email-kjwinchester@gmail.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Kevin Winchester
committed by
Ingo Molnar
Ingo Molnar
parent
ed3982cf37
commit
de0428a7ad
493
arch/x86/kernel/cpu/perf_event.h
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493
arch/x86/kernel/cpu/perf_event.h
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@@ -0,0 +1,493 @@
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/*
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* Performance events x86 architecture header
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*
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* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
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* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
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* Copyright (C) 2009 Jaswinder Singh Rajput
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* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
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* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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* Copyright (C) 2009 Google, Inc., Stephane Eranian
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*
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* For licencing details see kernel-base/COPYING
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*/
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#include <linux/perf_event.h>
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/*
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* | NHM/WSM | SNB |
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* register -------------------------------
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* | HT | no HT | HT | no HT |
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*-----------------------------------------
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* offcore | core | core | cpu | core |
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* lbr_sel | core | core | cpu | core |
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* ld_lat | cpu | core | cpu | core |
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*-----------------------------------------
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*
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* Given that there is a small number of shared regs,
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* we can pre-allocate their slot in the per-cpu
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* per-core reg tables.
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*/
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enum extra_reg_type {
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EXTRA_REG_NONE = -1, /* not used */
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EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
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EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
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EXTRA_REG_MAX /* number of entries needed */
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};
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struct event_constraint {
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union {
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unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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u64 idxmsk64;
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};
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u64 code;
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u64 cmask;
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int weight;
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};
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struct amd_nb {
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int nb_id; /* NorthBridge id */
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int refcnt; /* reference count */
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struct perf_event *owners[X86_PMC_IDX_MAX];
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struct event_constraint event_constraints[X86_PMC_IDX_MAX];
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};
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/* The maximal number of PEBS events: */
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#define MAX_PEBS_EVENTS 4
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/*
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* A debug store configuration.
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*
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* We only support architectures that use 64bit fields.
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*/
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struct debug_store {
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u64 bts_buffer_base;
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u64 bts_index;
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u64 bts_absolute_maximum;
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u64 bts_interrupt_threshold;
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u64 pebs_buffer_base;
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u64 pebs_index;
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u64 pebs_absolute_maximum;
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u64 pebs_interrupt_threshold;
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u64 pebs_event_reset[MAX_PEBS_EVENTS];
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};
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/*
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* Per register state.
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*/
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struct er_account {
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raw_spinlock_t lock; /* per-core: protect structure */
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u64 config; /* extra MSR config */
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u64 reg; /* extra MSR number */
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atomic_t ref; /* reference count */
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};
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/*
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* Per core/cpu state
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*
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* Used to coordinate shared registers between HT threads or
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* among events on a single PMU.
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*/
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struct intel_shared_regs {
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struct er_account regs[EXTRA_REG_MAX];
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int refcnt; /* per-core: #HT threads */
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unsigned core_id; /* per-core: core id */
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};
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#define MAX_LBR_ENTRIES 16
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struct cpu_hw_events {
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/*
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* Generic x86 PMC bits
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*/
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struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
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unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
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int enabled;
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int n_events;
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int n_added;
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int n_txn;
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int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
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u64 tags[X86_PMC_IDX_MAX];
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struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
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unsigned int group_flag;
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/*
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* Intel DebugStore bits
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*/
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struct debug_store *ds;
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u64 pebs_enabled;
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/*
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* Intel LBR bits
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*/
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int lbr_users;
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void *lbr_context;
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struct perf_branch_stack lbr_stack;
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struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
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/*
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* manage shared (per-core, per-cpu) registers
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* used on Intel NHM/WSM/SNB
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*/
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struct intel_shared_regs *shared_regs;
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/*
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* AMD specific bits
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*/
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struct amd_nb *amd_nb;
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void *kfree_on_online;
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};
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#define __EVENT_CONSTRAINT(c, n, m, w) {\
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{ .idxmsk64 = (n) }, \
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.code = (c), \
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.cmask = (m), \
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.weight = (w), \
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}
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#define EVENT_CONSTRAINT(c, n, m) \
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__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
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/*
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* Constraint on the Event code.
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*/
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#define INTEL_EVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
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/*
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* Constraint on the Event code + UMask + fixed-mask
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*
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* filter mask to validate fixed counter events.
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* the following filters disqualify for fixed counters:
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* - inv
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* - edge
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* - cnt-mask
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* The other filters are supported by fixed counters.
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* The any-thread option is supported starting with v3.
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*/
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#define FIXED_EVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
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/*
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* Constraint on the Event code + UMask
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*/
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#define INTEL_UEVENT_CONSTRAINT(c, n) \
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EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
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#define EVENT_CONSTRAINT_END \
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EVENT_CONSTRAINT(0, 0, 0)
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#define for_each_event_constraint(e, c) \
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for ((e) = (c); (e)->weight; (e)++)
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/*
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* Extra registers for specific events.
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*
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* Some events need large masks and require external MSRs.
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* Those extra MSRs end up being shared for all events on
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* a PMU and sometimes between PMU of sibling HT threads.
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* In either case, the kernel needs to handle conflicting
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* accesses to those extra, shared, regs. The data structure
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* to manage those registers is stored in cpu_hw_event.
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*/
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struct extra_reg {
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unsigned int event;
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unsigned int msr;
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u64 config_mask;
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u64 valid_mask;
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int idx; /* per_xxx->regs[] reg index */
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};
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#define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
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.event = (e), \
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.msr = (ms), \
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.config_mask = (m), \
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.valid_mask = (vm), \
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.idx = EXTRA_REG_##i \
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}
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#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
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EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
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#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
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union perf_capabilities {
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struct {
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u64 lbr_format:6;
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u64 pebs_trap:1;
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u64 pebs_arch_reg:1;
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u64 pebs_format:4;
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u64 smm_freeze:1;
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};
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u64 capabilities;
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};
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/*
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* struct x86_pmu - generic x86 pmu
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*/
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struct x86_pmu {
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/*
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* Generic x86 PMC bits
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*/
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const char *name;
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int version;
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int (*handle_irq)(struct pt_regs *);
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void (*disable_all)(void);
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void (*enable_all)(int added);
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void (*enable)(struct perf_event *);
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void (*disable)(struct perf_event *);
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int (*hw_config)(struct perf_event *event);
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int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
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unsigned eventsel;
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unsigned perfctr;
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u64 (*event_map)(int);
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int max_events;
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int num_counters;
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int num_counters_fixed;
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int cntval_bits;
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u64 cntval_mask;
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int apic;
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u64 max_period;
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struct event_constraint *
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(*get_event_constraints)(struct cpu_hw_events *cpuc,
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struct perf_event *event);
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void (*put_event_constraints)(struct cpu_hw_events *cpuc,
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struct perf_event *event);
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struct event_constraint *event_constraints;
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void (*quirks)(void);
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int perfctr_second_write;
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int (*cpu_prepare)(int cpu);
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void (*cpu_starting)(int cpu);
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void (*cpu_dying)(int cpu);
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void (*cpu_dead)(int cpu);
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/*
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* Intel Arch Perfmon v2+
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*/
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u64 intel_ctrl;
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union perf_capabilities intel_cap;
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/*
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* Intel DebugStore bits
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*/
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int bts, pebs;
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int bts_active, pebs_active;
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int pebs_record_size;
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void (*drain_pebs)(struct pt_regs *regs);
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struct event_constraint *pebs_constraints;
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/*
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* Intel LBR
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*/
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unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
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int lbr_nr; /* hardware stack size */
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/*
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* Extra registers for events
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*/
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struct extra_reg *extra_regs;
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unsigned int er_flags;
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};
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#define ERF_NO_HT_SHARING 1
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#define ERF_HAS_RSP_1 2
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extern struct x86_pmu x86_pmu __read_mostly;
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DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
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int x86_perf_event_set_period(struct perf_event *event);
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/*
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* Generalized hw caching related hw_event table, filled
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* in on a per model basis. A value of 0 means
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* 'not supported', -1 means 'hw_event makes no sense on
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* this CPU', any other value means the raw hw_event
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* ID.
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*/
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#define C(x) PERF_COUNT_HW_CACHE_##x
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extern u64 __read_mostly hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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extern u64 __read_mostly hw_cache_extra_regs
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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u64 x86_perf_event_update(struct perf_event *event);
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static inline int x86_pmu_addr_offset(int index)
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{
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int offset;
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/* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
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alternative_io(ASM_NOP2,
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"shll $1, %%eax",
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X86_FEATURE_PERFCTR_CORE,
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"=a" (offset),
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"a" (index));
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return offset;
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}
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static inline unsigned int x86_pmu_config_addr(int index)
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{
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return x86_pmu.eventsel + x86_pmu_addr_offset(index);
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}
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static inline unsigned int x86_pmu_event_addr(int index)
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{
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return x86_pmu.perfctr + x86_pmu_addr_offset(index);
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}
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int x86_setup_perfctr(struct perf_event *event);
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int x86_pmu_hw_config(struct perf_event *event);
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void x86_pmu_disable_all(void);
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static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
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u64 enable_mask)
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{
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if (hwc->extra_reg.reg)
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wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
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wrmsrl(hwc->config_base, hwc->config | enable_mask);
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}
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void x86_pmu_enable_all(int added);
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int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
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void x86_pmu_stop(struct perf_event *event, int flags);
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static inline void x86_pmu_disable_event(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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wrmsrl(hwc->config_base, hwc->config);
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}
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void x86_pmu_enable_event(struct perf_event *event);
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int x86_pmu_handle_irq(struct pt_regs *regs);
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extern struct event_constraint emptyconstraint;
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extern struct event_constraint unconstrained;
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#ifdef CONFIG_CPU_SUP_AMD
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int amd_pmu_init(void);
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#else /* CONFIG_CPU_SUP_AMD */
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static inline int amd_pmu_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_CPU_SUP_AMD */
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#ifdef CONFIG_CPU_SUP_INTEL
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int intel_pmu_save_and_restart(struct perf_event *event);
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struct event_constraint *
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x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
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struct intel_shared_regs *allocate_shared_regs(int cpu);
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int intel_pmu_init(void);
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void init_debug_store_on_cpu(int cpu);
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void fini_debug_store_on_cpu(int cpu);
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void release_ds_buffers(void);
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void reserve_ds_buffers(void);
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extern struct event_constraint bts_constraint;
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void intel_pmu_enable_bts(u64 config);
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void intel_pmu_disable_bts(void);
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int intel_pmu_drain_bts_buffer(void);
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extern struct event_constraint intel_core2_pebs_event_constraints[];
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extern struct event_constraint intel_atom_pebs_event_constraints[];
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extern struct event_constraint intel_nehalem_pebs_event_constraints[];
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extern struct event_constraint intel_westmere_pebs_event_constraints[];
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extern struct event_constraint intel_snb_pebs_event_constraints[];
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struct event_constraint *intel_pebs_constraints(struct perf_event *event);
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void intel_pmu_pebs_enable(struct perf_event *event);
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void intel_pmu_pebs_disable(struct perf_event *event);
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void intel_pmu_pebs_enable_all(void);
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void intel_pmu_pebs_disable_all(void);
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void intel_ds_init(void);
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void intel_pmu_lbr_reset(void);
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void intel_pmu_lbr_enable(struct perf_event *event);
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void intel_pmu_lbr_disable(struct perf_event *event);
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void intel_pmu_lbr_enable_all(void);
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void intel_pmu_lbr_disable_all(void);
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void intel_pmu_lbr_read(void);
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void intel_pmu_lbr_init_core(void);
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void intel_pmu_lbr_init_nhm(void);
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void intel_pmu_lbr_init_atom(void);
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int p4_pmu_init(void);
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int p6_pmu_init(void);
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#else /* CONFIG_CPU_SUP_INTEL */
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static inline void reserve_ds_buffers(void)
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{
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}
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static inline void release_ds_buffers(void)
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{
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}
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static inline int intel_pmu_init(void)
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{
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return 0;
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}
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static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
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{
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return NULL;
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}
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#endif /* CONFIG_CPU_SUP_INTEL */
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