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x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs

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According to AMD RDTSC can be synchronized through MFENCE.
Implement the necessary CPUID bit for that.

Cc: andreas.herrmann3@amd.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Andi Kleen
2008-01-30 13:32:37 +01:00
committed by Ingo Molnar
parent 27efeb6771
commit de4218634e
3 changed files with 6 additions and 2 deletions
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3
arch/x86/kernel/cpu/amd.c
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@@ -301,6 +301,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
/* K6s reports MCEs but don't actually have all the MSRs */ /* K6s reports MCEs but don't actually have all the MSRs */
if (c->x86 < 6) if (c->x86 < 6)
clear_bit(X86_FEATURE_MCE, c->x86_capability); clear_bit(X86_FEATURE_MCE, c->x86_capability);
if (cpu_has_xmm)
set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
} }
static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)

4
arch/x86/kernel/setup_64.c
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@@ -746,8 +746,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11) if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
set_cpu_cap(c, X86_FEATURE_K8); set_cpu_cap(c, X86_FEATURE_K8);
/* RDTSC can be speculated around */ /* MFENCE stops RDTSC speculation */
clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC); set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
/* Family 10 doesn't support C states in MWAIT so don't use it */ /* Family 10 doesn't support C states in MWAIT so don't use it */
if (c->x86 == 0x10 && !force_mwait) if (c->x86 == 0x10 && !force_mwait)

1
include/asm-x86/cpufeature.h
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@@ -79,6 +79,7 @@
/* 14 free */ /* 14 free */
#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */
#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */