KVM: PPC: Convert SRR0 and SRR1 to shared page
The SRR0 and SRR1 registers contain cached values of the PC and MSR respectively. They get written to by the hypervisor when an interrupt occurs or directly by the kernel. They are also used to tell the rfi(d) instruction where to jump to. Because it only gets touched on defined events that, it's very simple to share with the guest. Hypervisor and guest both have full r/w access. This patch converts all users of the current field to the shared page. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
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Avi Kivity
parent
5e030186df
commit
de7906c36c
@@ -64,7 +64,8 @@ void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu)
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printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
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printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
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printk("srr0: %08lx srr1: %08lx\n", vcpu->arch.srr0, vcpu->arch.srr1);
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printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
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vcpu->arch.shared->srr1);
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printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions);
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@@ -189,8 +190,8 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
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}
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if (allowed) {
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vcpu->arch.srr0 = vcpu->arch.pc;
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vcpu->arch.srr1 = vcpu->arch.shared->msr;
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vcpu->arch.shared->srr0 = vcpu->arch.pc;
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vcpu->arch.shared->srr1 = vcpu->arch.shared->msr;
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vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
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if (update_esr == true)
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vcpu->arch.esr = vcpu->arch.queued_esr;
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@@ -491,8 +492,8 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
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regs->lr = vcpu->arch.lr;
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regs->xer = kvmppc_get_xer(vcpu);
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regs->msr = vcpu->arch.shared->msr;
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regs->srr0 = vcpu->arch.srr0;
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regs->srr1 = vcpu->arch.srr1;
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regs->srr0 = vcpu->arch.shared->srr0;
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regs->srr1 = vcpu->arch.shared->srr1;
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regs->pid = vcpu->arch.pid;
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regs->sprg0 = vcpu->arch.sprg0;
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regs->sprg1 = vcpu->arch.sprg1;
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@@ -518,8 +519,8 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
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vcpu->arch.lr = regs->lr;
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kvmppc_set_xer(vcpu, regs->xer);
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kvmppc_set_msr(vcpu, regs->msr);
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vcpu->arch.srr0 = regs->srr0;
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vcpu->arch.srr1 = regs->srr1;
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vcpu->arch.shared->srr0 = regs->srr0;
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vcpu->arch.shared->srr1 = regs->srr1;
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vcpu->arch.sprg0 = regs->sprg0;
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vcpu->arch.sprg1 = regs->sprg1;
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vcpu->arch.sprg2 = regs->sprg2;
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