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sh: clock-cpg div4 set_rate() shift fix

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Make sure the div4 bitfield is shifted according
to the enable_bit value in sh_clk_div4_set_rate().

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
2010-02-19 09:12:00 +00:00
committed by Paul Mundt
parent 8c563a30cd
commit de7ca2144c
1 changed files with 2 additions and 2 deletions
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4
arch/sh/kernel/cpu/clock-cpg.c
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@@ -192,8 +192,8 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id
return idx; return idx;
value = __raw_readl(clk->enable_reg); value = __raw_readl(clk->enable_reg);
value &= ~0xf; value &= ~(0xf << clk->enable_bit);
value |= idx; value |= (idx << clk->enable_bit);
__raw_writel(value, clk->enable_reg); __raw_writel(value, clk->enable_reg);
return 0; return 0;