parisc: move include/asm-parisc to arch/parisc/include/asm
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Kyle McMartin
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Kyle McMartin
Kyle McMartin
parent
6c86cb8237
commit
deae26bf6a
294
arch/parisc/include/asm/pci.h
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294
arch/parisc/include/asm/pci.h
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#ifndef __ASM_PARISC_PCI_H
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#define __ASM_PARISC_PCI_H
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#include <asm/scatterlist.h>
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/*
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** HP PCI platforms generally support multiple bus adapters.
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** (workstations 1-~4, servers 2-~32)
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**
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** Newer platforms number the busses across PCI bus adapters *sparsely*.
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** E.g. 0, 8, 16, ...
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**
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** Under a PCI bus, most HP platforms support PPBs up to two or three
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** levels deep. See "Bit3" product line.
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*/
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#define PCI_MAX_BUSSES 256
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/* To be used as: mdelay(pci_post_reset_delay);
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*
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* post_reset is the time the kernel should stall to prevent anyone from
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* accessing the PCI bus once #RESET is de-asserted.
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* PCI spec somewhere says 1 second but with multi-PCI bus systems,
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* this makes the boot time much longer than necessary.
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* 20ms seems to work for all the HP PCI implementations to date.
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*/
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#define pci_post_reset_delay 50
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/*
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** pci_hba_data (aka H2P_OBJECT in HP/UX)
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**
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** This is the "common" or "base" data structure which HBA drivers
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** (eg Dino or LBA) are required to place at the top of their own
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** platform_data structure. I've heard this called "C inheritance" too.
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**
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** Data needed by pcibios layer belongs here.
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*/
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struct pci_hba_data {
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void __iomem *base_addr; /* aka Host Physical Address */
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const struct parisc_device *dev; /* device from PA bus walk */
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struct pci_bus *hba_bus; /* primary PCI bus below HBA */
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int hba_num; /* I/O port space access "key" */
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struct resource bus_num; /* PCI bus numbers */
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struct resource io_space; /* PIOP */
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struct resource lmmio_space; /* bus addresses < 4Gb */
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struct resource elmmio_space; /* additional bus addresses < 4Gb */
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struct resource gmmio_space; /* bus addresses > 4Gb */
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/* NOTE: Dino code assumes it can use *all* of the lmmio_space,
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* elmmio_space and gmmio_space as a contiguous array of
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* resources. This #define represents the array size */
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#define DINO_MAX_LMMIO_RESOURCES 3
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unsigned long lmmio_space_offset; /* CPU view - PCI view */
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void * iommu; /* IOMMU this device is under */
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/* REVISIT - spinlock to protect resources? */
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#define HBA_NAME_SIZE 16
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char io_name[HBA_NAME_SIZE];
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char lmmio_name[HBA_NAME_SIZE];
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char elmmio_name[HBA_NAME_SIZE];
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char gmmio_name[HBA_NAME_SIZE];
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};
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#define HBA_DATA(d) ((struct pci_hba_data *) (d))
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/*
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** We support 2^16 I/O ports per HBA. These are set up in the form
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** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
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** space address.
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*/
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#define HBA_PORT_SPACE_BITS 16
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#define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
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#define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
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#define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
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#define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
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#ifdef CONFIG_64BIT
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#define PCI_F_EXTEND 0xffffffff00000000UL
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#define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a)
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/* We need to know if an address is LMMMIO or GMMIO.
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* LMMIO requires mangling and GMMIO we must use as-is.
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*/
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static __inline__ int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
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{
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return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
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}
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/*
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** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
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** See pci.c for more conversions used by Generic PCI code.
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**
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** Platform characteristics/firmware guarantee that
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** (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
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** (2) PA_VIEW == IO_VIEW for GMMIO
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*/
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#define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \
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? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \
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: (a)) /* GMMIO */
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#define PCI_HOST_ADDR(hba,a) (((a) & PCI_F_EXTEND) == 0 \
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? (a) + hba->lmmio_space_offset \
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: (a))
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#else /* !CONFIG_64BIT */
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#define PCI_BUS_ADDR(hba,a) (a)
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#define PCI_HOST_ADDR(hba,a) (a)
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#define PCI_F_EXTEND 0UL
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#define PCI_IS_LMMIO(hba,a) (1) /* 32-bit doesn't support GMMIO */
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#endif /* !CONFIG_64BIT */
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/*
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** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
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** (This eliminates some of the warnings).
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*/
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struct pci_bus;
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struct pci_dev;
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/*
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* If the PCI device's view of memory is the same as the CPU's view of memory,
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* PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use
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* this boolean for bounce buffer decisions.
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*/
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#ifdef CONFIG_PA20
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/* All PA-2.0 machines have an IOMMU. */
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#define PCI_DMA_BUS_IS_PHYS 0
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#define parisc_has_iommu() do { } while (0)
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#else
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#if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA)
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extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */
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#define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys
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#define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0)
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#else
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#define PCI_DMA_BUS_IS_PHYS 1
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#define parisc_has_iommu() do { } while (0)
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#endif
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#endif /* !CONFIG_PA20 */
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/*
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** Most PCI devices (eg Tulip, NCR720) also export the same registers
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** to both MMIO and I/O port space. Due to poor performance of I/O Port
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** access under HP PCI bus adapters, strongly recommend the use of MMIO
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** address space.
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**
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** While I'm at it more PA programming notes:
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**
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** 1) MMIO stores (writes) are posted operations. This means the processor
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** gets an "ACK" before the write actually gets to the device. A read
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** to the same device (or typically the bus adapter above it) will
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** force in-flight write transaction(s) out to the targeted device
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** before the read can complete.
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**
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** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
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** respect to DMA on all platforms. Ie PIO data can reach the processor
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** before in-flight DMA reaches memory. Since most SMP PA platforms
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** are I/O coherent, it generally doesn't matter...but sometimes
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** it does.
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**
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** I've helped device driver writers debug both types of problems.
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*/
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struct pci_port_ops {
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u8 (*inb) (struct pci_hba_data *hba, u16 port);
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u16 (*inw) (struct pci_hba_data *hba, u16 port);
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u32 (*inl) (struct pci_hba_data *hba, u16 port);
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void (*outb) (struct pci_hba_data *hba, u16 port, u8 data);
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void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
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void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
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};
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struct pci_bios_ops {
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void (*init)(void);
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void (*fixup_bus)(struct pci_bus *bus);
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};
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
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__u32 LEN_NAME;
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#define pci_unmap_addr(PTR, ADDR_NAME) \
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((PTR)->ADDR_NAME)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
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(((PTR)->ADDR_NAME) = (VAL))
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#define pci_unmap_len(PTR, LEN_NAME) \
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((PTR)->LEN_NAME)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/*
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** Stuff declared in arch/parisc/kernel/pci.c
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*/
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extern struct pci_port_ops *pci_port;
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extern struct pci_bios_ops *pci_bios;
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#ifdef CONFIG_PCI
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extern void pcibios_register_hba(struct pci_hba_data *);
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extern void pcibios_set_master(struct pci_dev *);
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#else
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static inline void pcibios_register_hba(struct pci_hba_data *x)
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{
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}
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#endif
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/*
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* pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
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* 0 == check if bridge is numbered before re-numbering.
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* 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
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*
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* We *should* set this to zero for "legacy" platforms and one
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* for PAT platforms.
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*
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* But legacy platforms also need to renumber the busses below a Host
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* Bus controller. Adding a 4-port Tulip card on the first PCI root
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* bus of a C200 resulted in the secondary bus being numbered as 1.
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* The second PCI host bus controller's root bus had already been
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* assigned bus number 1 by firmware and sysfs complained.
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*
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* Firmware isn't doing anything wrong here since each controller
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* is its own PCI domain. It's simpler and easier for us to renumber
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* the busses rather than treat each Dino as a separate PCI domain.
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* Eventually, we may want to introduce PCI domains for Superdome or
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* rp7420/8420 boxes and then revisit this issue.
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*/
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#define pcibios_assign_all_busses() (1)
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#define pcibios_scan_all_fns(a, b) (0)
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#define PCIBIOS_MIN_IO 0x10
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#define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
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/* export the pci_ DMA API in terms of the dma_ one */
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#include <asm-generic/pci-dma-compat.h>
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_MULTIPLE;
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*strategy_parameter = cacheline_size;
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}
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#endif
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extern void
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pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res);
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extern void
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pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region);
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static inline struct resource *
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pcibios_select_root(struct pci_dev *pdev, struct resource *res)
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{
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struct resource *root = NULL;
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if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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if (res->flags & IORESOURCE_MEM)
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root = &iomem_resource;
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return root;
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}
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static inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't need to penalize isa irq's */
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}
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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return channel ? 15 : 14;
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}
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#endif /* __ASM_PARISC_PCI_H */
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