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powerpc/mm: Add MMU features for TLB reservation & Paired MAS registers

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Support for TLB reservation (or TLB Write Conditional) and Paired MAS
registers are optional for a processor implementation so we handle
them via MMU feature sections.

We currently only used paired MAS registers to access the full RPN + perm
bits that are kept in MAS7||MAS3.  We assume that if an implementation has
hardware page table at this time it also implements in TLB reservations.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Kumar Gala
2009-08-24 15:52:48 +00:00
committed by Benjamin Herrenschmidt
parent 23e55f92d4
commit df5d6ecf81
2 changed files with 46 additions and 1 deletions
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9
arch/powerpc/include/asm/mmu.h
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@@ -58,6 +58,15 @@
*/
#define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000)
/* Enable use of TLB reservation. Processor should support tlbsrx.
* instruction and MAS0[WQ].
*/
#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
/* Use paired MAS registers (MAS7||MAS3, etc.)
*/
#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
#ifndef __ASSEMBLY__
#include <asm/cputable.h>