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More AP / SP bits for the 34K, the Malta bits and things. Still wants

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a little polishing.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2005-07-14 15:57:16 +00:00
parent 86071b637d
commit e01402b115
18 changed files with 2332 additions and 139 deletions
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3
arch/mips/mm/c-r4k.c
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@ -1228,8 +1228,7 @@ void __init ld_mmu_r4xx0(void)
struct cpuinfo_mips *c = &current_cpu_data;
/* Default cache error handler for R4000 and R5000 family */
memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80);
memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
set_uncached_handler (0x100, &except_vec2_generic, 0x80);
probe_pcache();
setup_scache();

5
arch/mips/mm/c-sb1.c
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@ -502,9 +502,8 @@ void ld_mmu_sb1(void)
extern char handle_vec2_sb1;
/* Special cache error handler for SB1 */
memcpy((void *)(CAC_BASE + 0x100), &except_vec2_sb1, 0x80);
memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_sb1, 0x80);
memcpy((void *)CKSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
memcpy((void *)KSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
probe_cache_sizes();