Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (63 commits) ARM: PL08x: cleanup comments Update CONFIG_MD_RAID6_PQ to CONFIG_RAID6_PQ in drivers/dma/iop-adma.c ARM: PL08x: fix a warning Fix dmaengine_submit() return type dmaengine: at_hdmac: fix race while monitoring channel status dmaengine: at_hdmac: flags located in first descriptor dmaengine: at_hdmac: use subsys_initcall instead of module_init dmaengine: at_hdmac: no need set ACK in new descriptor dmaengine: at_hdmac: trivial add precision to unmapping comment dmaengine: at_hdmac: use dma_address to program DMA hardware pch_dma: support new device ML7213 IOH ARM: PL08x: prevent dma_set_runtime_config() reconfiguring memcpy channels ARM: PL08x: allow dma_set_runtime_config() to return errors ARM: PL08x: fix locking between prepare function and submit function ARM: PL08x: introduce 'phychan_hold' to hold on to physical channels ARM: PL08x: put txd's on the pending list in pl08x_tx_submit() ARM: PL08x: rename 'desc_list' as 'pend_list' ARM: PL08x: implement unmapping of memcpy buffers ARM: PL08x: store prep_* flags in async_tx structure ARM: PL08x: shrink srcbus/dstbus in txd structure ...
This commit is contained in:
Linus Torvalds
@ -12,7 +12,6 @@
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*
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* Please credit ARM.com
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* Documentation: ARM DDI 0196D
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*
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*/
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#ifndef AMBA_PL08X_H
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@ -22,6 +21,15 @@
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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struct pl08x_lli;
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struct pl08x_driver_data;
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/* Bitmasks for selecting AHB ports for DMA transfers */
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enum {
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PL08X_AHB1 = (1 << 0),
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PL08X_AHB2 = (1 << 1)
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};
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/**
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* struct pl08x_channel_data - data structure to pass info between
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* platform and PL08x driver regarding channel configuration
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@ -46,8 +54,10 @@
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* @circular_buffer: whether the buffer passed in is circular and
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* shall simply be looped round round (like a record baby round
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* round round round)
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* @single: the device connected to this channel will request single
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* DMA transfers, not bursts. (Bursts are default.)
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* @single: the device connected to this channel will request single DMA
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* transfers, not bursts. (Bursts are default.)
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* @periph_buses: the device connected to this channel is accessible via
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* these buses (use PL08X_AHB1 | PL08X_AHB2).
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*/
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struct pl08x_channel_data {
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char *bus_id;
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@ -55,10 +65,10 @@ struct pl08x_channel_data {
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int max_signal;
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u32 muxval;
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u32 cctl;
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u32 ccfg;
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dma_addr_t addr;
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bool circular_buffer;
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bool single;
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u8 periph_buses;
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};
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/**
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@ -67,24 +77,23 @@ struct pl08x_channel_data {
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* @addr: current address
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* @maxwidth: the maximum width of a transfer on this bus
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* @buswidth: the width of this bus in bytes: 1, 2 or 4
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* @fill_bytes: bytes required to fill to the next bus memory
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* boundary
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* @fill_bytes: bytes required to fill to the next bus memory boundary
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*/
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struct pl08x_bus_data {
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dma_addr_t addr;
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u8 maxwidth;
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u8 buswidth;
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u32 fill_bytes;
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size_t fill_bytes;
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};
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/**
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* struct pl08x_phy_chan - holder for the physical channels
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* @id: physical index to this channel
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* @lock: a lock to use when altering an instance of this struct
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* @signal: the physical signal (aka channel) serving this
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* physical channel right now
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* @serving: the virtual channel currently being served by this
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* physical channel
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* @signal: the physical signal (aka channel) serving this physical channel
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* right now
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* @serving: the virtual channel currently being served by this physical
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* channel
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*/
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struct pl08x_phy_chan {
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unsigned int id;
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@ -92,11 +101,6 @@ struct pl08x_phy_chan {
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spinlock_t lock;
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int signal;
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struct pl08x_dma_chan *serving;
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u32 csrc;
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u32 cdst;
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u32 clli;
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u32 cctl;
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u32 ccfg;
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};
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/**
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@ -108,26 +112,23 @@ struct pl08x_txd {
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struct dma_async_tx_descriptor tx;
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struct list_head node;
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enum dma_data_direction direction;
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struct pl08x_bus_data srcbus;
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struct pl08x_bus_data dstbus;
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int len;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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size_t len;
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dma_addr_t llis_bus;
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void *llis_va;
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struct pl08x_channel_data *cd;
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bool active;
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struct pl08x_lli *llis_va;
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/* Default cctl value for LLIs */
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u32 cctl;
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/*
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* Settings to be put into the physical channel when we
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* trigger this txd
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* trigger this txd. Other registers are in llis_va[0].
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*/
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u32 csrc;
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u32 cdst;
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u32 clli;
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u32 cctl;
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u32 ccfg;
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};
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/**
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* struct pl08x_dma_chan_state - holds the PL08x specific virtual
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* channel states
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* struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
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* states
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* @PL08X_CHAN_IDLE: the channel is idle
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* @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
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* channel and is running a transfer on it
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@ -147,6 +148,8 @@ enum pl08x_dma_chan_state {
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* struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
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* @chan: wrappped abstract channel
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* @phychan: the physical channel utilized by this channel, if there is one
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* @phychan_hold: if non-zero, hold on to the physical channel even if we
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* have no pending entries
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* @tasklet: tasklet scheduled by the IRQ to handle actual work etc
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* @name: name of channel
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* @cd: channel platform data
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@ -154,53 +157,49 @@ enum pl08x_dma_chan_state {
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* @runtime_direction: current direction of this channel according to
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* runtime config
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* @lc: last completed transaction on this channel
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* @desc_list: queued transactions pending on this channel
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* @pend_list: queued transactions pending on this channel
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* @at: active transaction on this channel
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* @lockflags: sometimes we let a lock last between two function calls,
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* especially prep/submit, and then we need to store the IRQ flags
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* in the channel state, here
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* @lock: a lock for this channel data
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* @host: a pointer to the host (internal use)
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* @state: whether the channel is idle, paused, running etc
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* @slave: whether this channel is a device (slave) or for memcpy
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* @waiting: a TX descriptor on this channel which is waiting for
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* a physical channel to become available
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* @waiting: a TX descriptor on this channel which is waiting for a physical
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* channel to become available
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*/
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struct pl08x_dma_chan {
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struct dma_chan chan;
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struct pl08x_phy_chan *phychan;
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int phychan_hold;
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struct tasklet_struct tasklet;
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char *name;
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struct pl08x_channel_data *cd;
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dma_addr_t runtime_addr;
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enum dma_data_direction runtime_direction;
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atomic_t last_issued;
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dma_cookie_t lc;
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struct list_head desc_list;
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struct list_head pend_list;
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struct pl08x_txd *at;
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unsigned long lockflags;
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spinlock_t lock;
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void *host;
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struct pl08x_driver_data *host;
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enum pl08x_dma_chan_state state;
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bool slave;
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struct pl08x_txd *waiting;
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};
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/**
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* struct pl08x_platform_data - the platform configuration for the
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* PL08x PrimeCells.
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* struct pl08x_platform_data - the platform configuration for the PL08x
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* PrimeCells.
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* @slave_channels: the channels defined for the different devices on the
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* platform, all inclusive, including multiplexed channels. The available
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* physical channels will be multiplexed around these signals as they
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* are requested, just enumerate all possible channels.
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* @get_signal: request a physical signal to be used for a DMA
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* transfer immediately: if there is some multiplexing or similar blocking
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* the use of the channel the transfer can be denied by returning
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* less than zero, else it returns the allocated signal number
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* physical channels will be multiplexed around these signals as they are
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* requested, just enumerate all possible channels.
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* @get_signal: request a physical signal to be used for a DMA transfer
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* immediately: if there is some multiplexing or similar blocking the use
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* of the channel the transfer can be denied by returning less than zero,
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* else it returns the allocated signal number
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* @put_signal: indicate to the platform that this physical signal is not
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* running any DMA transfer and multiplexing can be recycled
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* @bus_bit_lli: Bit[0] of the address indicated which AHB bus master the
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* LLI addresses are on 0/1 Master 1/2.
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* @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
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* @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
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*/
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struct pl08x_platform_data {
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struct pl08x_channel_data *slave_channels;
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@ -208,6 +207,8 @@ struct pl08x_platform_data {
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struct pl08x_channel_data memcpy_channel;
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int (*get_signal)(struct pl08x_dma_chan *);
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void (*put_signal)(struct pl08x_dma_chan *);
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u8 lli_buses;
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u8 mem_buses;
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};
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#ifdef CONFIG_AMBA_PL08X
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