iwlagn: move the mapping ac to queue / fifo to transport
This mapping is transport related. This allows us to remove the notion of tx queue from the tx path in the upper layer. iwl_wake_any_queue moved to transport layer since it needs to access these mappings. The TX API is nicer now: int (*tx)(struct iwl_trans *trans, struct sk_buff *skb, struct iwl_device_cmd *dev_cmd, u8 ctx, u8 sta_id); Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
committed by
John W. Linville
parent
dfa2bdbab7
commit
e13c0c59e0
@@ -835,7 +835,8 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
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*/
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*/
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if (ctx->last_tx_rejected) {
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if (ctx->last_tx_rejected) {
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ctx->last_tx_rejected = false;
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ctx->last_tx_rejected = false;
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iwl_wake_any_queue(priv, ctx);
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iwl_trans_wake_any_queue(trans(priv),
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ctx->ctxid);
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}
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}
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ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
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ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
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@@ -278,14 +278,11 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
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struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
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struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
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struct iwl_device_cmd *dev_cmd = NULL;
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struct iwl_device_cmd *dev_cmd = NULL;
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struct iwl_tx_cmd *tx_cmd;
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struct iwl_tx_cmd *tx_cmd;
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int txq_id;
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u16 seq_number = 0;
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__le16 fc;
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__le16 fc;
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u8 hdr_len;
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u8 hdr_len;
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u16 len;
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u16 len;
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u8 sta_id;
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u8 sta_id;
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u8 tid = 0;
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unsigned long flags;
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unsigned long flags;
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bool is_agg = false;
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bool is_agg = false;
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@@ -343,50 +340,9 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
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iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
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iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
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}
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}
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/*
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* Send this frame after DTIM -- there's a special queue
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* reserved for this for contexts that support AP mode.
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*/
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if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
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txq_id = ctx->mcast_queue;
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/*
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* The microcode will clear the more data
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* bit in the last frame it transmits.
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*/
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hdr->frame_control |=
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cpu_to_le16(IEEE80211_FCTL_MOREDATA);
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} else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
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txq_id = IWL_AUX_QUEUE;
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else
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txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
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/* irqs already disabled/saved above when locking priv->shrd->lock */
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/* irqs already disabled/saved above when locking priv->shrd->lock */
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spin_lock(&priv->shrd->sta_lock);
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spin_lock(&priv->shrd->sta_lock);
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if (ieee80211_is_data_qos(fc)) {
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u8 *qc = NULL;
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struct iwl_tid_data *tid_data;
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qc = ieee80211_get_qos_ctl(hdr);
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tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
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tid_data = &priv->shrd->tid_data[sta_id][tid];
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if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
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goto drop_unlock_sta;
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seq_number = tid_data->seq_number;
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seq_number &= IEEE80211_SCTL_SEQ;
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hdr->seq_ctrl = hdr->seq_ctrl &
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cpu_to_le16(IEEE80211_SCTL_FRAG);
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hdr->seq_ctrl |= cpu_to_le16(seq_number);
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seq_number += 0x10;
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/* aggregation is on for this <sta,tid> */
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if (info->flags & IEEE80211_TX_CTL_AMPDU &&
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tid_data->agg.state == IWL_AGG_ON) {
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txq_id = tid_data->agg.txq_id;
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is_agg = true;
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}
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}
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dev_cmd = kmem_cache_alloc(priv->tx_cmd_pool, GFP_ATOMIC);
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dev_cmd = kmem_cache_alloc(priv->tx_cmd_pool, GFP_ATOMIC);
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if (unlikely(!dev_cmd))
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if (unlikely(!dev_cmd))
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@@ -416,16 +372,9 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
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info->driver_data[0] = ctx;
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info->driver_data[0] = ctx;
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info->driver_data[1] = dev_cmd;
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info->driver_data[1] = dev_cmd;
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if (iwl_trans_tx(trans(priv), skb, dev_cmd, txq_id, fc, is_agg))
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if (iwl_trans_tx(trans(priv), skb, dev_cmd, ctx->ctxid, sta_id))
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goto drop_unlock_sta;
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goto drop_unlock_sta;
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if (ieee80211_is_data_qos(fc)) {
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priv->shrd->tid_data[sta_id][tid].tfds_in_queue++;
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if (!ieee80211_has_morefrags(fc))
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priv->shrd->tid_data[sta_id][tid].seq_number =
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seq_number;
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}
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spin_unlock(&priv->shrd->sta_lock);
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spin_unlock(&priv->shrd->sta_lock);
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spin_unlock_irqrestore(&priv->shrd->lock, flags);
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spin_unlock_irqrestore(&priv->shrd->lock, flags);
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@@ -617,24 +617,6 @@ static int iwl_alloc_fw_desc(struct iwl_priv *priv, struct fw_desc *desc,
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static void iwl_init_context(struct iwl_priv *priv, u32 ucode_flags)
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static void iwl_init_context(struct iwl_priv *priv, u32 ucode_flags)
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{
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{
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static const u8 iwlagn_bss_ac_to_fifo[] = {
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IWL_TX_FIFO_VO,
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IWL_TX_FIFO_VI,
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IWL_TX_FIFO_BE,
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IWL_TX_FIFO_BK,
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};
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static const u8 iwlagn_bss_ac_to_queue[] = {
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0, 1, 2, 3,
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};
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static const u8 iwlagn_pan_ac_to_fifo[] = {
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IWL_TX_FIFO_VO_IPAN,
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IWL_TX_FIFO_VI_IPAN,
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IWL_TX_FIFO_BE_IPAN,
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IWL_TX_FIFO_BK_IPAN,
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};
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static const u8 iwlagn_pan_ac_to_queue[] = {
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7, 6, 5, 4,
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};
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int i;
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int i;
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/*
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/*
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@@ -656,8 +638,6 @@ static void iwl_init_context(struct iwl_priv *priv, u32 ucode_flags)
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priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
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priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
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priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
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priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
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priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
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priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
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priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
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priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
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priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
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priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
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BIT(NL80211_IFTYPE_ADHOC);
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BIT(NL80211_IFTYPE_ADHOC);
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priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
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priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
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@@ -677,9 +657,6 @@ static void iwl_init_context(struct iwl_priv *priv, u32 ucode_flags)
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priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
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priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
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priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
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priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
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priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
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priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
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priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
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priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
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priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
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priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
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priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
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BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
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BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
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@@ -244,13 +244,6 @@ struct iwl_channel_info {
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#define IWL_DEFAULT_CMD_QUEUE_NUM 4
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#define IWL_DEFAULT_CMD_QUEUE_NUM 4
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#define IWL_IPAN_CMD_QUEUE_NUM 9
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#define IWL_IPAN_CMD_QUEUE_NUM 9
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/*
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* This queue number is required for proper operation
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* because the ucode will stop/start the scheduler as
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* required.
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*/
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#define IWL_IPAN_MCAST_QUEUE 8
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#define IEEE80211_DATA_LEN 2304
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#define IEEE80211_DATA_LEN 2304
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#define IEEE80211_4ADDR_LEN 30
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#define IEEE80211_4ADDR_LEN 30
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#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
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#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
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@@ -965,10 +958,6 @@ struct iwl_notification_wait {
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struct iwl_rxon_context {
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struct iwl_rxon_context {
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struct ieee80211_vif *vif;
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struct ieee80211_vif *vif;
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const u8 *ac_to_fifo;
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const u8 *ac_to_queue;
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u8 mcast_queue;
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/*
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/*
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* We could use the vif to indicate active, but we
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* We could use the vif to indicate active, but we
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* also need it to be active during disabling when
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* also need it to be active during disabling when
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@@ -113,19 +113,6 @@ static inline void iwl_stop_queue(struct iwl_priv *priv,
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ieee80211_stop_queue(priv->hw, ac);
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ieee80211_stop_queue(priv->hw, ac);
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}
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}
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static inline void iwl_wake_any_queue(struct iwl_priv *priv,
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struct iwl_rxon_context *ctx)
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{
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u8 ac;
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for (ac = 0; ac < AC_NUM; ac++) {
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IWL_DEBUG_INFO(priv, "Queue Status: Q[%d] %s\n",
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ac, (atomic_read(&priv->queue_stop_count[ac]) > 0)
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? "stopped" : "awake");
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iwl_wake_queue(priv, &priv->txq[ctx->ac_to_queue[ac]]);
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}
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}
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#ifdef ieee80211_stop_queue
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#ifdef ieee80211_stop_queue
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#undef ieee80211_stop_queue
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#undef ieee80211_stop_queue
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#endif
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#endif
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@@ -699,7 +699,7 @@ static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
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ctx->active.bssid_addr))
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ctx->active.bssid_addr))
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continue;
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continue;
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ctx->last_tx_rejected = false;
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ctx->last_tx_rejected = false;
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iwl_wake_any_queue(priv, ctx);
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iwl_trans_wake_any_queue(trans(priv), ctx->ctxid);
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}
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}
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}
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}
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@@ -107,6 +107,13 @@ struct iwl_dma_ptr {
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size_t size;
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size_t size;
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};
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};
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/*
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* This queue number is required for proper operation
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* because the ucode will stop/start the scheduler as
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* required.
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*/
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#define IWL_IPAN_MCAST_QUEUE 8
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/**
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/**
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* struct iwl_trans_pcie - PCIe transport specific data
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* struct iwl_trans_pcie - PCIe transport specific data
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* @rxq: all the RX queue data
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* @rxq: all the RX queue data
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@@ -115,6 +122,9 @@ struct iwl_dma_ptr {
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* @scd_base_addr: scheduler sram base address in SRAM
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* @scd_base_addr: scheduler sram base address in SRAM
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* @scd_bc_tbls: pointer to the byte count table of the scheduler
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* @scd_bc_tbls: pointer to the byte count table of the scheduler
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* @kw: keep warm address
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* @kw: keep warm address
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* @ac_to_fifo: to what fifo is a specifc AC mapped ?
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* @ac_to_queue: to what tx queue is a specifc AC mapped ?
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* @mcast_queue:
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*/
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*/
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struct iwl_trans_pcie {
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struct iwl_trans_pcie {
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struct iwl_rx_queue rxq;
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struct iwl_rx_queue rxq;
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@@ -136,6 +146,10 @@ struct iwl_trans_pcie {
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u32 scd_base_addr;
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u32 scd_base_addr;
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struct iwl_dma_ptr scd_bc_tbls;
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struct iwl_dma_ptr scd_bc_tbls;
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struct iwl_dma_ptr kw;
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struct iwl_dma_ptr kw;
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const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
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const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
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u8 mcast_queue[NUM_IWL_RXON_CTX];
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};
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};
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#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
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#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
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@@ -424,10 +424,12 @@ void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
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scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
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scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
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}
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}
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static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
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static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
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u8 ctx, u16 tid)
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{
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{
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const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
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if (likely(tid < ARRAY_SIZE(tid_to_ac)))
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if (likely(tid < ARRAY_SIZE(tid_to_ac)))
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return ctx->ac_to_fifo[tid_to_ac[tid]];
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return ac_to_fifo[tid_to_ac[tid]];
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/* no support for TIDs 8-15 yet */
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/* no support for TIDs 8-15 yet */
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return -EINVAL;
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return -EINVAL;
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@@ -451,7 +453,7 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
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if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
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return;
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return;
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tx_fifo = get_fifo_from_tid(&priv->contexts[ctx], tid);
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tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
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if (WARN_ON(tx_fifo < 0)) {
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if (WARN_ON(tx_fifo < 0)) {
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IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
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IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
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return;
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return;
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@@ -714,12 +714,75 @@ static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
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return ret;
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return ret;
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}
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}
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#define IWL_AC_UNSET -1
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struct queue_to_fifo_ac {
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s8 fifo, ac;
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};
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static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
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{ IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
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{ IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
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{ IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
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{ IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
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{ IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
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{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
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{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
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{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
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{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
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{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
||||||
|
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
|
||||||
|
{ IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
|
||||||
|
{ IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
|
||||||
|
{ IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
|
||||||
|
{ IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
|
||||||
|
{ IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
|
||||||
|
{ IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
|
||||||
|
{ IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
|
||||||
|
{ IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
|
||||||
|
{ IWL_TX_FIFO_BE_IPAN, 2, },
|
||||||
|
{ IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
|
||||||
|
{ IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
|
||||||
|
};
|
||||||
|
|
||||||
|
static const u8 iwlagn_bss_ac_to_fifo[] = {
|
||||||
|
IWL_TX_FIFO_VO,
|
||||||
|
IWL_TX_FIFO_VI,
|
||||||
|
IWL_TX_FIFO_BE,
|
||||||
|
IWL_TX_FIFO_BK,
|
||||||
|
};
|
||||||
|
static const u8 iwlagn_bss_ac_to_queue[] = {
|
||||||
|
0, 1, 2, 3,
|
||||||
|
};
|
||||||
|
static const u8 iwlagn_pan_ac_to_fifo[] = {
|
||||||
|
IWL_TX_FIFO_VO_IPAN,
|
||||||
|
IWL_TX_FIFO_VI_IPAN,
|
||||||
|
IWL_TX_FIFO_BE_IPAN,
|
||||||
|
IWL_TX_FIFO_BK_IPAN,
|
||||||
|
};
|
||||||
|
static const u8 iwlagn_pan_ac_to_queue[] = {
|
||||||
|
7, 6, 5, 4,
|
||||||
|
};
|
||||||
|
|
||||||
static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
|
static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
struct iwl_priv *priv = priv(trans);
|
struct iwl_priv *priv = priv(trans);
|
||||||
|
struct iwl_trans_pcie *trans_pcie =
|
||||||
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||||
|
|
||||||
priv->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
|
priv->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
|
||||||
|
trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
|
||||||
|
trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
|
||||||
|
|
||||||
|
trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
|
||||||
|
trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
|
||||||
|
|
||||||
|
trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
|
||||||
|
trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
|
||||||
|
|
||||||
if ((hw_params(priv).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
|
if ((hw_params(priv).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
|
||||||
iwl_trans_pcie_prepare_card_hw(trans)) {
|
iwl_trans_pcie_prepare_card_hw(trans)) {
|
||||||
@@ -773,39 +836,6 @@ static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
|
|||||||
iwl_write_prph(bus(trans), SCD_TXFACT, mask);
|
iwl_write_prph(bus(trans), SCD_TXFACT, mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
#define IWL_AC_UNSET -1
|
|
||||||
|
|
||||||
struct queue_to_fifo_ac {
|
|
||||||
s8 fifo, ac;
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
|
|
||||||
{ IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
|
|
||||||
{ IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
|
|
||||||
{ IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
|
|
||||||
{ IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
|
|
||||||
{ IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
|
|
||||||
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
||||||
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
||||||
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
||||||
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
||||||
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
||||||
{ IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
|
|
||||||
{ IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
|
|
||||||
{ IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
|
|
||||||
{ IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
|
|
||||||
{ IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
|
|
||||||
{ IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
|
|
||||||
{ IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
|
|
||||||
{ IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
|
|
||||||
{ IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
|
|
||||||
{ IWL_TX_FIFO_BE_IPAN, 2, },
|
|
||||||
{ IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
|
|
||||||
{ IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
|
|
||||||
};
|
|
||||||
static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
|
static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
|
||||||
{
|
{
|
||||||
const struct queue_to_fifo_ac *queue_to_fifo;
|
const struct queue_to_fifo_ac *queue_to_fifo;
|
||||||
@@ -1012,22 +1042,75 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
|
|||||||
iwl_apm_stop(priv(trans));
|
iwl_apm_stop(priv(trans));
|
||||||
}
|
}
|
||||||
|
|
||||||
static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
||||||
struct iwl_device_cmd *dev_cmd, int txq_id,
|
struct iwl_device_cmd *dev_cmd, u8 ctx, u8 sta_id)
|
||||||
__le16 fc, bool ampdu)
|
|
||||||
{
|
{
|
||||||
struct iwl_tx_queue *txq = &priv->txq[txq_id];
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||||
struct iwl_queue *q = &txq->q;
|
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
|
||||||
|
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
||||||
struct iwl_tx_cmd *tx_cmd = &dev_cmd->cmd.tx;
|
struct iwl_tx_cmd *tx_cmd = &dev_cmd->cmd.tx;
|
||||||
struct iwl_cmd_meta *out_meta;
|
struct iwl_cmd_meta *out_meta;
|
||||||
|
struct iwl_tx_queue *txq;
|
||||||
|
struct iwl_queue *q;
|
||||||
|
|
||||||
dma_addr_t phys_addr = 0;
|
dma_addr_t phys_addr = 0;
|
||||||
dma_addr_t txcmd_phys;
|
dma_addr_t txcmd_phys;
|
||||||
dma_addr_t scratch_phys;
|
dma_addr_t scratch_phys;
|
||||||
u16 len, firstlen, secondlen;
|
u16 len, firstlen, secondlen;
|
||||||
|
u16 seq_number = 0;
|
||||||
u8 wait_write_ptr = 0;
|
u8 wait_write_ptr = 0;
|
||||||
|
u8 txq_id;
|
||||||
|
u8 tid = 0;
|
||||||
|
bool is_agg = false;
|
||||||
|
__le16 fc = hdr->frame_control;
|
||||||
u8 hdr_len = ieee80211_hdrlen(fc);
|
u8 hdr_len = ieee80211_hdrlen(fc);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Send this frame after DTIM -- there's a special queue
|
||||||
|
* reserved for this for contexts that support AP mode.
|
||||||
|
*/
|
||||||
|
if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
|
||||||
|
txq_id = trans_pcie->mcast_queue[ctx];
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The microcode will clear the more data
|
||||||
|
* bit in the last frame it transmits.
|
||||||
|
*/
|
||||||
|
hdr->frame_control |=
|
||||||
|
cpu_to_le16(IEEE80211_FCTL_MOREDATA);
|
||||||
|
} else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
|
||||||
|
txq_id = IWL_AUX_QUEUE;
|
||||||
|
else
|
||||||
|
txq_id =
|
||||||
|
trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
|
||||||
|
|
||||||
|
if (ieee80211_is_data_qos(fc)) {
|
||||||
|
u8 *qc = NULL;
|
||||||
|
struct iwl_tid_data *tid_data;
|
||||||
|
qc = ieee80211_get_qos_ctl(hdr);
|
||||||
|
tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
|
||||||
|
tid_data = &trans->shrd->tid_data[sta_id][tid];
|
||||||
|
|
||||||
|
if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
seq_number = tid_data->seq_number;
|
||||||
|
seq_number &= IEEE80211_SCTL_SEQ;
|
||||||
|
hdr->seq_ctrl = hdr->seq_ctrl &
|
||||||
|
cpu_to_le16(IEEE80211_SCTL_FRAG);
|
||||||
|
hdr->seq_ctrl |= cpu_to_le16(seq_number);
|
||||||
|
seq_number += 0x10;
|
||||||
|
/* aggregation is on for this <sta,tid> */
|
||||||
|
if (info->flags & IEEE80211_TX_CTL_AMPDU &&
|
||||||
|
tid_data->agg.state == IWL_AGG_ON) {
|
||||||
|
txq_id = tid_data->agg.txq_id;
|
||||||
|
is_agg = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
txq = &priv(trans)->txq[txq_id];
|
||||||
|
q = &txq->q;
|
||||||
|
|
||||||
/* Set up driver data for this TFD */
|
/* Set up driver data for this TFD */
|
||||||
txq->skbs[q->write_ptr] = skb;
|
txq->skbs[q->write_ptr] = skb;
|
||||||
txq->cmd[q->write_ptr] = dev_cmd;
|
txq->cmd[q->write_ptr] = dev_cmd;
|
||||||
@@ -1058,10 +1141,10 @@ static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
|||||||
|
|
||||||
/* Physical address of this Tx command's header (not MAC header!),
|
/* Physical address of this Tx command's header (not MAC header!),
|
||||||
* within command buffer array. */
|
* within command buffer array. */
|
||||||
txcmd_phys = dma_map_single(priv->bus->dev,
|
txcmd_phys = dma_map_single(bus(trans)->dev,
|
||||||
&dev_cmd->hdr, firstlen,
|
&dev_cmd->hdr, firstlen,
|
||||||
DMA_BIDIRECTIONAL);
|
DMA_BIDIRECTIONAL);
|
||||||
if (unlikely(dma_mapping_error(priv->bus->dev, txcmd_phys)))
|
if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
|
||||||
return -1;
|
return -1;
|
||||||
dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
|
dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
|
||||||
dma_unmap_len_set(out_meta, len, firstlen);
|
dma_unmap_len_set(out_meta, len, firstlen);
|
||||||
@@ -1077,10 +1160,10 @@ static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
|||||||
* if any (802.11 null frames have no payload). */
|
* if any (802.11 null frames have no payload). */
|
||||||
secondlen = skb->len - hdr_len;
|
secondlen = skb->len - hdr_len;
|
||||||
if (secondlen > 0) {
|
if (secondlen > 0) {
|
||||||
phys_addr = dma_map_single(priv->bus->dev, skb->data + hdr_len,
|
phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
|
||||||
secondlen, DMA_TO_DEVICE);
|
secondlen, DMA_TO_DEVICE);
|
||||||
if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
|
if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
|
||||||
dma_unmap_single(priv->bus->dev,
|
dma_unmap_single(bus(trans)->dev,
|
||||||
dma_unmap_addr(out_meta, mapping),
|
dma_unmap_addr(out_meta, mapping),
|
||||||
dma_unmap_len(out_meta, len),
|
dma_unmap_len(out_meta, len),
|
||||||
DMA_BIDIRECTIONAL);
|
DMA_BIDIRECTIONAL);
|
||||||
@@ -1089,36 +1172,35 @@ static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Attach buffers to TFD */
|
/* Attach buffers to TFD */
|
||||||
iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, txcmd_phys,
|
iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
|
||||||
firstlen, 1);
|
|
||||||
if (secondlen > 0)
|
if (secondlen > 0)
|
||||||
iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, phys_addr,
|
iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
|
||||||
secondlen, 0);
|
secondlen, 0);
|
||||||
|
|
||||||
scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
|
scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
|
||||||
offsetof(struct iwl_tx_cmd, scratch);
|
offsetof(struct iwl_tx_cmd, scratch);
|
||||||
|
|
||||||
/* take back ownership of DMA buffer to enable update */
|
/* take back ownership of DMA buffer to enable update */
|
||||||
dma_sync_single_for_cpu(priv->bus->dev, txcmd_phys, firstlen,
|
dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
|
||||||
DMA_BIDIRECTIONAL);
|
DMA_BIDIRECTIONAL);
|
||||||
tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
|
tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
|
||||||
tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
|
tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
|
||||||
|
|
||||||
IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
|
IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
|
||||||
le16_to_cpu(dev_cmd->hdr.sequence));
|
le16_to_cpu(dev_cmd->hdr.sequence));
|
||||||
IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
|
IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
|
||||||
iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
|
iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
|
||||||
iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
|
iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
|
||||||
|
|
||||||
/* Set up entry for this TFD in Tx byte-count array */
|
/* Set up entry for this TFD in Tx byte-count array */
|
||||||
if (ampdu)
|
if (is_agg)
|
||||||
iwl_trans_txq_update_byte_cnt_tbl(trans(priv), txq,
|
iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
|
||||||
le16_to_cpu(tx_cmd->len));
|
le16_to_cpu(tx_cmd->len));
|
||||||
|
|
||||||
dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
|
dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
|
||||||
DMA_BIDIRECTIONAL);
|
DMA_BIDIRECTIONAL);
|
||||||
|
|
||||||
trace_iwlwifi_dev_tx(priv,
|
trace_iwlwifi_dev_tx(priv(trans),
|
||||||
&((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
|
&((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
|
||||||
sizeof(struct iwl_tfd),
|
sizeof(struct iwl_tfd),
|
||||||
&dev_cmd->hdr, firstlen,
|
&dev_cmd->hdr, firstlen,
|
||||||
@@ -1126,7 +1208,14 @@ static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
|||||||
|
|
||||||
/* Tell device the write index *just past* this latest filled TFD */
|
/* Tell device the write index *just past* this latest filled TFD */
|
||||||
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
|
||||||
iwl_txq_update_write_ptr(trans(priv), txq);
|
iwl_txq_update_write_ptr(trans, txq);
|
||||||
|
|
||||||
|
if (ieee80211_is_data_qos(fc)) {
|
||||||
|
trans->shrd->tid_data[sta_id][tid].tfds_in_queue++;
|
||||||
|
if (!ieee80211_has_morefrags(fc))
|
||||||
|
trans->shrd->tid_data[sta_id][tid].seq_number =
|
||||||
|
seq_number;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* At this point the frame is "transmitted" successfully
|
* At this point the frame is "transmitted" successfully
|
||||||
@@ -1137,9 +1226,9 @@ static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
|
|||||||
if (iwl_queue_space(q) < q->high_mark) {
|
if (iwl_queue_space(q) < q->high_mark) {
|
||||||
if (wait_write_ptr) {
|
if (wait_write_ptr) {
|
||||||
txq->need_update = 1;
|
txq->need_update = 1;
|
||||||
iwl_txq_update_write_ptr(trans(priv), txq);
|
iwl_txq_update_write_ptr(trans, txq);
|
||||||
} else {
|
} else {
|
||||||
iwl_stop_queue(priv, txq);
|
iwl_stop_queue(priv(trans), txq);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return 0;
|
return 0;
|
||||||
@@ -1262,6 +1351,23 @@ static int iwl_trans_pcie_resume(struct iwl_trans *trans)
|
|||||||
|
|
||||||
#endif /* CONFIG_PM */
|
#endif /* CONFIG_PM */
|
||||||
|
|
||||||
|
static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
|
||||||
|
u8 ctx)
|
||||||
|
{
|
||||||
|
u8 ac, txq_id;
|
||||||
|
struct iwl_trans_pcie *trans_pcie =
|
||||||
|
IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||||
|
|
||||||
|
for (ac = 0; ac < AC_NUM; ac++) {
|
||||||
|
txq_id = trans_pcie->ac_to_queue[ctx][ac];
|
||||||
|
IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n",
|
||||||
|
ac,
|
||||||
|
(atomic_read(&priv(trans)->queue_stop_count[ac]) > 0)
|
||||||
|
? "stopped" : "awake");
|
||||||
|
iwl_wake_queue(priv(trans), &priv(trans)->txq[txq_id]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
const struct iwl_trans_ops trans_ops_pcie;
|
const struct iwl_trans_ops trans_ops_pcie;
|
||||||
|
|
||||||
static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
|
static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
|
||||||
@@ -1842,6 +1948,7 @@ const struct iwl_trans_ops trans_ops_pcie = {
|
|||||||
.stop_device = iwl_trans_pcie_stop_device,
|
.stop_device = iwl_trans_pcie_stop_device,
|
||||||
|
|
||||||
.tx_start = iwl_trans_pcie_tx_start,
|
.tx_start = iwl_trans_pcie_tx_start,
|
||||||
|
.wake_any_queue = iwl_trans_pcie_wake_any_queue,
|
||||||
|
|
||||||
.send_cmd = iwl_trans_pcie_send_cmd,
|
.send_cmd = iwl_trans_pcie_send_cmd,
|
||||||
.send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
|
.send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
|
||||||
|
@@ -88,6 +88,7 @@ struct iwl_device_cmd;
|
|||||||
* probe.
|
* probe.
|
||||||
* @tx_start: starts and configures all the Tx fifo - usually done once the fw
|
* @tx_start: starts and configures all the Tx fifo - usually done once the fw
|
||||||
* is alive.
|
* is alive.
|
||||||
|
* @wake_any_queue: wake all the queues of a specfic context IWL_RXON_CTX_*
|
||||||
* @stop_device:stops the whole device (embedded CPU put to reset)
|
* @stop_device:stops the whole device (embedded CPU put to reset)
|
||||||
* @send_cmd:send a host command
|
* @send_cmd:send a host command
|
||||||
* @send_cmd_pdu:send a host command: flags can be CMD_*
|
* @send_cmd_pdu:send a host command: flags can be CMD_*
|
||||||
@@ -113,13 +114,14 @@ struct iwl_trans_ops {
|
|||||||
void (*stop_device)(struct iwl_trans *trans);
|
void (*stop_device)(struct iwl_trans *trans);
|
||||||
void (*tx_start)(struct iwl_trans *trans);
|
void (*tx_start)(struct iwl_trans *trans);
|
||||||
|
|
||||||
|
void (*wake_any_queue)(struct iwl_trans *trans, u8 ctx);
|
||||||
|
|
||||||
int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
|
int (*send_cmd)(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
|
||||||
|
|
||||||
int (*send_cmd_pdu)(struct iwl_trans *trans, u8 id, u32 flags, u16 len,
|
int (*send_cmd_pdu)(struct iwl_trans *trans, u8 id, u32 flags, u16 len,
|
||||||
const void *data);
|
const void *data);
|
||||||
int (*tx)(struct iwl_priv *priv, struct sk_buff *skb,
|
int (*tx)(struct iwl_trans *trans, struct sk_buff *skb,
|
||||||
struct iwl_device_cmd *dev_cmd,
|
struct iwl_device_cmd *dev_cmd, u8 ctx, u8 sta_id);
|
||||||
int txq_id, __le16 fc, bool ampdu);
|
|
||||||
void (*reclaim)(struct iwl_trans *trans, int txq_id, int ssn,
|
void (*reclaim)(struct iwl_trans *trans, int txq_id, int ssn,
|
||||||
u32 status, struct sk_buff_head *skbs);
|
u32 status, struct sk_buff_head *skbs);
|
||||||
|
|
||||||
@@ -178,6 +180,12 @@ static inline void iwl_trans_tx_start(struct iwl_trans *trans)
|
|||||||
trans->ops->tx_start(trans);
|
trans->ops->tx_start(trans);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline void iwl_trans_wake_any_queue(struct iwl_trans *trans, u8 ctx)
|
||||||
|
{
|
||||||
|
trans->ops->wake_any_queue(trans, ctx);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
static inline int iwl_trans_send_cmd(struct iwl_trans *trans,
|
static inline int iwl_trans_send_cmd(struct iwl_trans *trans,
|
||||||
struct iwl_host_cmd *cmd)
|
struct iwl_host_cmd *cmd)
|
||||||
{
|
{
|
||||||
@@ -191,10 +199,9 @@ static inline int iwl_trans_send_cmd_pdu(struct iwl_trans *trans, u8 id,
|
|||||||
}
|
}
|
||||||
|
|
||||||
static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
static inline int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
|
||||||
struct iwl_device_cmd *dev_cmd,
|
struct iwl_device_cmd *dev_cmd, u8 ctx, u8 sta_id)
|
||||||
int txq_id, __le16 fc, bool ampdu)
|
|
||||||
{
|
{
|
||||||
return trans->ops->tx(priv(trans), skb, dev_cmd, txq_id, fc, ampdu);
|
return trans->ops->tx(trans, skb, dev_cmd, ctx, sta_id);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void iwl_trans_reclaim(struct iwl_trans *trans, int txq_id,
|
static inline void iwl_trans_reclaim(struct iwl_trans *trans, int txq_id,
|
||||||
|
Reference in New Issue
Block a user