powerpc/44x: Adding PCI-E support for PowerPC 460SX based SOC.
Add support for PCI-e on the AMCC 460SX boards Signed-off-by: Tirumala Marri <tmarri@amcc.com> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Tirumala Marri
committed by
Josh Boyer
Josh Boyer
parent
1ed31d6db9
commit
e2efc09e52
@@ -234,10 +234,132 @@
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has-inverted-stacr-oc;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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has-new-stacr-staopc;
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};
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};
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};
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PCIE0: pciex@d00000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
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primary;
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port = <0x0>; /* port number */
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reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
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0x0000000c 0x10000000 0x00001000>; /* Registers */
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dcr-reg = <0x100 0x020>;
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sdr-base = <0x300>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
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0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
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/* This drives busses 10 to 0x1f */
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bus-range = <0x10 0x1f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
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0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
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0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
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0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
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};
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PCIE1: pciex@d20000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
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primary;
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port = <0x1>; /* port number */
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reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
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0x0000000c 0x10001000 0x00001000>; /* Registers */
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dcr-reg = <0x120 0x020>;
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sdr-base = <0x340>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
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0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
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/* This drives busses 10 to 0x1f */
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bus-range = <0x20 0x2f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
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0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
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0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
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0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
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};
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PCIE2: pciex@d40000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
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primary;
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port = <0x2>; /* port number */
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reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
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0x0000000c 0x10002000 0x00001000>; /* Registers */
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dcr-reg = <0x140 0x020>;
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sdr-base = <0x370>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
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0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
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/* This drives busses 10 to 0x1f */
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bus-range = <0x30 0x3f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
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0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
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0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
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0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
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};
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};
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};
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};
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chosen {
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chosen {
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linux,stdout-path = "/plb/opb/serial@ef600200";
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linux,stdout-path = "/plb/opb/serial@ef600200";
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};
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};
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@@ -974,6 +974,123 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
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.setup_utl = ppc460ex_pciex_init_utl,
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.setup_utl = ppc460ex_pciex_init_utl,
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};
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};
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static int __init ppc460sx_pciex_core_init(struct device_node *np)
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{
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/* HSS drive amplitude */
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mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
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mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
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/* HSS TX pre-emphasis */
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mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
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mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
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/* HSS TX calibration control */
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mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
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mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
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mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
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/* HSS TX slew control */
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mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
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mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
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mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
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udelay(100);
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/* De-assert PLLRESET */
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dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
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/* Reset DL, UTL, GPL before configuration */
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mtdcri(SDR0, PESDR0_460SX_RCSSET,
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PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
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mtdcri(SDR0, PESDR1_460SX_RCSSET,
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PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
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mtdcri(SDR0, PESDR2_460SX_RCSSET,
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PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
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udelay(100);
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/*
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* If bifurcation is not enabled, u-boot would have disabled the
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* third PCIe port
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*/
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if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
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0x00000001)) {
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printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
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printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
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return 3;
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}
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printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
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return 2;
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}
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static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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{
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if (port->endpoint)
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dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
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0x01000000, 0);
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else
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dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
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0, 0x01000000);
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/*Gen-1*/
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mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000);
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dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
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(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
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PESDRx_RCSSET_RSTPYN);
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port->has_ibpre = 1;
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return 0;
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}
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static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
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{
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/* Max 128 Bytes */
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out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
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return 0;
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}
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static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
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.core_init = ppc460sx_pciex_core_init,
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.port_init_hw = ppc460sx_pciex_init_port_hw,
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.setup_utl = ppc460sx_pciex_init_utl,
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};
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#endif /* CONFIG_44x */
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#endif /* CONFIG_44x */
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#ifdef CONFIG_40x
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#ifdef CONFIG_40x
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@@ -1089,6 +1206,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
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}
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}
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if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
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if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
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ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
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ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
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if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
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ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
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#endif /* CONFIG_44x */
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#endif /* CONFIG_44x */
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#ifdef CONFIG_40x
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#ifdef CONFIG_40x
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if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
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if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
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@@ -323,6 +323,64 @@
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#define PESDR0_460EX_IHS1 0x036C
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#define PESDR0_460EX_IHS1 0x036C
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#define PESDR0_460EX_IHS2 0x036D
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#define PESDR0_460EX_IHS2 0x036D
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/*
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* 460SX addtional DCRs
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*/
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#define PESDRn_460SX_RCEI 0x02
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#define PESDR0_460SX_HSSL0DAMP 0x320
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#define PESDR0_460SX_HSSL1DAMP 0x321
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#define PESDR0_460SX_HSSL2DAMP 0x322
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#define PESDR0_460SX_HSSL3DAMP 0x323
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#define PESDR0_460SX_HSSL4DAMP 0x324
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#define PESDR0_460SX_HSSL5DAMP 0x325
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#define PESDR0_460SX_HSSL6DAMP 0x326
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#define PESDR0_460SX_HSSL7DAMP 0x327
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#define PESDR1_460SX_HSSL0DAMP 0x354
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#define PESDR1_460SX_HSSL1DAMP 0x355
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#define PESDR1_460SX_HSSL2DAMP 0x356
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#define PESDR1_460SX_HSSL3DAMP 0x357
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||||||
|
#define PESDR2_460SX_HSSL0DAMP 0x384
|
||||||
|
#define PESDR2_460SX_HSSL1DAMP 0x385
|
||||||
|
#define PESDR2_460SX_HSSL2DAMP 0x386
|
||||||
|
#define PESDR2_460SX_HSSL3DAMP 0x387
|
||||||
|
|
||||||
|
#define PESDR0_460SX_HSSL0COEFA 0x328
|
||||||
|
#define PESDR0_460SX_HSSL1COEFA 0x329
|
||||||
|
#define PESDR0_460SX_HSSL2COEFA 0x32A
|
||||||
|
#define PESDR0_460SX_HSSL3COEFA 0x32B
|
||||||
|
#define PESDR0_460SX_HSSL4COEFA 0x32C
|
||||||
|
#define PESDR0_460SX_HSSL5COEFA 0x32D
|
||||||
|
#define PESDR0_460SX_HSSL6COEFA 0x32E
|
||||||
|
#define PESDR0_460SX_HSSL7COEFA 0x32F
|
||||||
|
|
||||||
|
#define PESDR1_460SX_HSSL0COEFA 0x358
|
||||||
|
#define PESDR1_460SX_HSSL1COEFA 0x359
|
||||||
|
#define PESDR1_460SX_HSSL2COEFA 0x35A
|
||||||
|
#define PESDR1_460SX_HSSL3COEFA 0x35B
|
||||||
|
|
||||||
|
#define PESDR2_460SX_HSSL0COEFA 0x388
|
||||||
|
#define PESDR2_460SX_HSSL1COEFA 0x389
|
||||||
|
#define PESDR2_460SX_HSSL2COEFA 0x38A
|
||||||
|
#define PESDR2_460SX_HSSL3COEFA 0x38B
|
||||||
|
|
||||||
|
#define PESDR0_460SX_HSSL1CALDRV 0x339
|
||||||
|
#define PESDR1_460SX_HSSL1CALDRV 0x361
|
||||||
|
#define PESDR2_460SX_HSSL1CALDRV 0x391
|
||||||
|
|
||||||
|
#define PESDR0_460SX_HSSSLEW 0x338
|
||||||
|
#define PESDR1_460SX_HSSSLEW 0x360
|
||||||
|
#define PESDR2_460SX_HSSSLEW 0x390
|
||||||
|
|
||||||
|
#define PESDR0_460SX_HSSCTLSET 0x31E
|
||||||
|
#define PESDR1_460SX_HSSCTLSET 0x352
|
||||||
|
#define PESDR2_460SX_HSSCTLSET 0x382
|
||||||
|
|
||||||
|
#define PESDR0_460SX_RCSSET 0x304
|
||||||
|
#define PESDR1_460SX_RCSSET 0x344
|
||||||
|
#define PESDR2_460SX_RCSSET 0x374
|
||||||
/*
|
/*
|
||||||
* Of the above, some are common offsets from the base
|
* Of the above, some are common offsets from the base
|
||||||
*/
|
*/
|
||||||
|
|||||||
Reference in New Issue
Block a user