sh: Add support for SH7706/SH7710/SH7343 CPUs.
This adds support for the aforementioned CPU subtypes, and cleans up some build issues encountered as a result. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
@ -192,7 +192,7 @@
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#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
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defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
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defined (CONFIG_CPU_SUBTYPE_SH7751)
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defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
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#define SCI_ERI_IRQ 23
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#define SCI_RXI_IRQ 24
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#define SCI_TXI_IRQ 25
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@ -207,6 +207,7 @@
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#define SCIF0_IPR_POS 3
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#define SCIF0_PRIORITY 3
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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#define SCIF_ERI_IRQ 56
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@ -261,9 +262,12 @@
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#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
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# define ONCHIP_NR_IRQS 32
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#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705)
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# define ONCHIP_NR_IRQS 64 // Actually 61
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
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# define ONCHIP_NR_IRQS 104
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
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# define ONCHIP_NR_IRQS 48 // Actually 44
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#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
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@ -275,7 +279,8 @@
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#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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# define ONCHIP_NR_IRQS 144
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#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH73180)
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defined(CONFIG_CPU_SUBTYPE_SH73180) || \
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defined(CONFIG_CPU_SUBTYPE_SH7343)
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# define ONCHIP_NR_IRQS 109
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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# define ONCHIP_NR_IRQS 111
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@ -476,8 +481,10 @@ extern int ipr_irq_demux(int irq);
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#define INTC_ICR 0xfffffee0UL
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710)
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#define INTC_IRR0 0xa4000004UL
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#define INTC_IRR1 0xa4000006UL
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#define INTC_IRR2 0xa4000008UL
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@ -496,8 +503,105 @@ extern int ipr_irq_demux(int irq);
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#define INTC_IPRF 0xa4080000UL
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#define INTC_IPRG 0xa4080002UL
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#define INTC_IPRH 0xa4080004UL
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#endif
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
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/* Interrupt Controller Registers */
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#undef INTC_IPRA
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#undef INTC_IPRB
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#define INTC_IPRA 0xA414FEE2UL
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#define INTC_IPRB 0xA414FEE4UL
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#define INTC_IPRF 0xA4080000UL
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#define INTC_IPRG 0xA4080002UL
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#define INTC_IPRH 0xA4080004UL
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#define INTC_IPRI 0xA4080006UL
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#undef INTC_ICR0
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#undef INTC_ICR1
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#define INTC_ICR0 0xA414FEE0UL
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#define INTC_ICR1 0xA4140010UL
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#define INTC_IRR0 0xa4000004UL
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#define INTC_IRR1 0xa4000006UL
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#define INTC_IRR2 0xa4000008UL
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#define INTC_IRR3 0xa400000AUL
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#define INTC_IRR4 0xa400000CUL
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#define INTC_IRR5 0xa4080020UL
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#define INTC_IRR7 0xa4080024UL
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#define INTC_IRR8 0xa4080026UL
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/* Interrupt numbers */
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#define TIMER2_IRQ 18
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#define TIMER2_IPR_ADDR INTC_IPRA
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#define TIMER2_IPR_POS 1
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#define TIMER2_PRIORITY 2
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/* WDT */
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#define WDT_IRQ 27
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#define WDT_IPR_ADDR INTC_IPRB
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#define WDT_IPR_POS 3
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#define WDT_PRIORITY 2
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#define SCIF0_ERI_IRQ 52
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#define SCIF0_RXI_IRQ 53
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#define SCIF0_BRI_IRQ 54
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#define SCIF0_TXI_IRQ 55
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#define SCIF0_IPR_ADDR INTC_IPRE
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#define SCIF0_IPR_POS 2
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#define SCIF0_PRIORITY 3
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#define DMTE4_IRQ 76
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#define DMTE5_IRQ 77
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#define DMA2_IPR_ADDR INTC_IPRF
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#define DMA2_IPR_POS 2
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#define DMA2_PRIORITY 7
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#define IPSEC_IRQ 79
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#define IPSEC_IPR_ADDR INTC_IPRF
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#define IPSEC_IPR_POS 3
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#define IPSEC_PRIORITY 3
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/* EDMAC */
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#define EDMAC0_IRQ 80
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#define EDMAC0_IPR_ADDR INTC_IPRG
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#define EDMAC0_IPR_POS 3
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#define EDMAC0_PRIORITY 3
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#define EDMAC1_IRQ 81
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#define EDMAC1_IPR_ADDR INTC_IPRG
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#define EDMAC1_IPR_POS 2
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#define EDMAC1_PRIORITY 3
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#define EDMAC2_IRQ 82
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#define EDMAC2_IPR_ADDR INTC_IPRG
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#define EDMAC2_IPR_POS 1
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#define EDMAC2_PRIORITY 3
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/* SIOF */
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#define SIOF0_ERI_IRQ 96
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#define SIOF0_TXI_IRQ 97
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#define SIOF0_RXI_IRQ 98
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#define SIOF0_CCI_IRQ 99
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#define SIOF0_IPR_ADDR INTC_IPRH
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#define SIOF0_IPR_POS 0
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#define SIOF0_PRIORITY 7
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#define SIOF1_ERI_IRQ 100
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#define SIOF1_TXI_IRQ 101
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#define SIOF1_RXI_IRQ 102
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#define SIOF1_CCI_IRQ 103
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#define SIOF1_IPR_ADDR INTC_IPRI
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#define SIOF1_IPR_POS 1
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#define SIOF1_PRIORITY 7
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#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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#define PORT_PACR 0xa4050100UL
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#define PORT_PBCR 0xa4050102UL
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#define PORT_PCCR 0xa4050104UL
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#define PORT_PETCR 0xa4050106UL
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#define PORT_PADR 0xa4050120UL
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#define PORT_PBDR 0xa4050122UL
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#define PORT_PCDR 0xa4050124UL
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#else
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#define PORT_PACR 0xa4000100UL
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#define PORT_PBCR 0xa4000102UL
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#define PORT_PCCR 0xa4000104UL
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@ -506,6 +610,7 @@ extern int ipr_irq_demux(int irq);
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#define PORT_PBDR 0xa4000122UL
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#define PORT_PCDR 0xa4000124UL
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#define PORT_PFDR 0xa400012aUL
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#endif
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#define IRQ0_IRQ 32
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#define IRQ1_IRQ 33
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@ -599,6 +704,8 @@ void intc2_add_clear_irq(int irq, int (*fn)(int));
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#endif
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extern int shmse_irq_demux(int irq);
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static inline int generic_irq_demux(int irq)
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{
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return irq;
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@ -614,4 +721,8 @@ static inline int generic_irq_demux(int irq)
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#include <asm/irq-sh73180.h>
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7343)
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#include <asm/irq-sh7343.h>
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#endif
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#endif /* __ASM_SH_IRQ_H */
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