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MIPS: Alchemy: fix wait function

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Only an interrupt can wake the core from 'wait', enable interrupts
locally before executing 'wait'.

[ralf@linux-mips.org: This leave the race between an interrupt that's
setting TIF_NEED_RESCHEd and entering the WAIT status. but at least it's
going to bring Alchemy back from the dead, so I'm going to apply this
patch.]

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5408/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
2013-06-08 19:15:41 +00:00
committed by Ralf Baechle
parent 317ddd256b
commit e63a24ddc7
1 changed files with 7 additions and 6 deletions
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13
arch/mips/kernel/idle.c
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@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
} }
/* /*
* The Au1xxx wait is available only if using 32khz counter or * Au1 'wait' is only useful when the 32kHz counter is used as timer,
* external timer source, but specifically not CP0 Counter. * since coreclock (and the cp0 counter) stops upon executing it. Only an
* alchemy/common/time.c may override cpu_wait! * interrupt can wake it, so they must be enabled before entering idle modes.
*/ */
static void au1k_wait(void) static void au1k_wait(void)
{ {
unsigned long c0status = read_c0_status() | 1; /* irqs on */
__asm__( __asm__(
" .set mips3 \n" " .set mips3 \n"
" cache 0x14, 0(%0) \n" " cache 0x14, 0(%0) \n"
" cache 0x14, 32(%0) \n" " cache 0x14, 32(%0) \n"
" sync \n" " sync \n"
" nop \n" " mtc0 %1, $12 \n" /* wr c0status */
" wait \n" " wait \n"
" nop \n" " nop \n"
" nop \n" " nop \n"
" nop \n" " nop \n"
" nop \n" " nop \n"
" .set mips0 \n" " .set mips0 \n"
: : "r" (au1k_wait)); : : "r" (au1k_wait), "r" (c0status));
local_irq_enable();
} }
static int __initdata nowait; static int __initdata nowait;