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nios2: flush_tlb_mm flush only the pid

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Currently flush_tlb_mm flushes the entire TLB. Switch it to doing a
PID aware flush. This also improves the readibility of flush_tlb_pid.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Nicholas Piggin 2018-11-05 10:51:44 +08:00 committed by Ley Foon Tan
parent 58fd476678
commit e71c99fe8d
1 changed files with 14 additions and 12 deletions
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26
arch/nios2/mm/tlb.c
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@ -39,18 +39,6 @@ static unsigned long pteaddr_invalid(unsigned long addr)
return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2;
}
/*
* All entries common to a mm share an asid. To effectively flush these
* entries, we just bump the asid.
*/
void flush_tlb_mm(struct mm_struct *mm)
{
if (current->mm == mm)
flush_tlb_all();
else
memset(&mm->context, 0, sizeof(mm_context_t));
}
/*
* This one is only used for pages with the global bit set so we don't care
* much about the ASID.
@ -233,6 +221,20 @@ void flush_tlb_pid(unsigned long pid)
WRCTL(CTL_TLBMISC, org_misc);
}
/*
* All entries common to a mm share an asid. To effectively flush these
* entries, we just bump the asid.
*/
void flush_tlb_mm(struct mm_struct *mm)
{
if (current->mm == mm) {
unsigned long mmu_pid = get_pid_from_context(&mm->context);
flush_tlb_pid(mmu_pid);
} else {
memset(&mm->context, 0, sizeof(mm_context_t));
}
}
void flush_tlb_all(void)
{
unsigned long addr = 0;