avr32: Generic clockevents support
This combines three patches from David Brownell: * avr32: tclib support * avr32: simplify clocksources * avr32: Turn count/compare into a oneshot clockevent device Register both TC blocks (instead of just the first one) so that the AT32/AT91 tclib code will pick them up (instead of just the avr32-only PIT-style clocksource). Rename the first one and its resources appropriately. More cleanups to the cycle counter clocksource code - Disable all the weak symbol magic; remove the AVR32-only TCB-based clocksource code (source and header). - Mark the __init code properly. - Don't forget to report IRQF_TIMER. - Make the system work properly with this clocksource, by preventing use of the CPU "idle" sleep state in the idle loop when it's used. Package the avr32 count/compare timekeeping support as a oneshot clockevent device, so it supports NO_HZ and high res timers. This means it also supports plugging in other clockevent devices and clocksources. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This commit is contained in:
David Brownell
committed by
Haavard Skinnemoen
Haavard Skinnemoen
parent
7e59128f31
commit
e723ff666a
@@ -1,16 +1,12 @@
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/*
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* Copyright (C) 2004-2007 Atmel Corporation
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*
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* Based on MIPS implementation arch/mips/kernel/time.c
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/time.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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@@ -27,13 +23,10 @@
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#include <asm/io.h>
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#include <asm/sections.h>
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/* how many counter cycles in a jiffy? */
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static u32 cycles_per_jiffy;
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#include <asm/arch/pm.h>
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/* the count value for the next timer interrupt */
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static u32 expirelo;
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cycle_t __weak read_cycle_count(void)
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static cycle_t read_cycle_count(void)
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{
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return (cycle_t)sysreg_read(COUNT);
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}
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@@ -42,10 +35,11 @@ cycle_t __weak read_cycle_count(void)
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* The architectural cycle count registers are a fine clocksource unless
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* the system idle loop use sleep states like "idle": the CPU cycles
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* measured by COUNT (and COMPARE) don't happen during sleep states.
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* Their duration also changes if cpufreq changes the CPU clock rate.
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* So we rate the clocksource using COUNT as very low quality.
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*/
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struct clocksource __weak clocksource_avr32 = {
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.name = "avr32",
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static struct clocksource counter = {
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.name = "avr32_counter",
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.rating = 50,
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.read = read_cycle_count,
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.mask = CLOCKSOURCE_MASK(32),
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@@ -53,152 +47,109 @@ struct clocksource __weak clocksource_avr32 = {
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
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struct irqaction timer_irqaction = {
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED,
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.name = "timer",
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};
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static void avr32_timer_ack(void)
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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u32 count;
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/* Ack this timer interrupt and set the next one */
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expirelo += cycles_per_jiffy;
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/* setting COMPARE to 0 stops the COUNT-COMPARE */
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if (expirelo == 0) {
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sysreg_write(COMPARE, expirelo + 1);
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} else {
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sysreg_write(COMPARE, expirelo);
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}
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/* Check to see if we have missed any timer interrupts */
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count = sysreg_read(COUNT);
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if ((count - expirelo) < 0x7fffffff) {
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expirelo = count + cycles_per_jiffy;
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sysreg_write(COMPARE, expirelo);
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}
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}
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int __weak avr32_hpt_init(void)
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{
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int ret;
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unsigned long mult, shift, count_hz;
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count_hz = clk_get_rate(boot_cpu_data.clk);
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shift = clocksource_avr32.shift;
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mult = clocksource_hz2mult(count_hz, shift);
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clocksource_avr32.mult = mult;
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{
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u64 tmp;
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tmp = TICK_NSEC;
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tmp <<= shift;
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tmp += mult / 2;
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do_div(tmp, mult);
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cycles_per_jiffy = tmp;
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}
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ret = setup_irq(0, &timer_irqaction);
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if (ret) {
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pr_debug("timer: could not request IRQ 0: %d\n", ret);
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return -ENODEV;
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}
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printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
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"%lu.%03lu MHz\n",
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((count_hz + 500) / 1000) / 1000,
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((count_hz + 500) / 1000) % 1000);
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return 0;
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}
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/*
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* Taken from MIPS c0_hpt_timer_init().
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*
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* The reason COUNT is written twice is probably to make sure we don't get any
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* timer interrupts while we are messing with the counter.
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*/
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int __weak avr32_hpt_start(void)
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{
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u32 count = sysreg_read(COUNT);
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expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
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sysreg_write(COUNT, expirelo - cycles_per_jiffy);
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sysreg_write(COMPARE, expirelo);
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sysreg_write(COUNT, count);
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return 0;
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}
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/*
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* local_timer_interrupt() does profiling and process accounting on a
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* per-CPU basis.
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*
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* In UP mode, it is invoked from the (global) timer_interrupt.
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*/
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void local_timer_interrupt(int irq, void *dev_id)
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{
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if (current->pid)
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profile_tick(CPU_PROFILING);
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update_process_times(user_mode(get_irq_regs()));
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}
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irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
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{
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/* ack timer interrupt and try to set next interrupt */
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avr32_timer_ack();
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struct clock_event_device *evdev = dev_id;
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/*
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* Call the generic timer interrupt handler
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* Disable the interrupt until the clockevent subsystem
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* reprograms it.
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*/
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write_seqlock(&xtime_lock);
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do_timer(1);
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write_sequnlock(&xtime_lock);
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/*
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* In UP mode, we call local_timer_interrupt() to do profiling
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* and process accounting.
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*
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* SMP is not supported yet.
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*/
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local_timer_interrupt(irq, dev_id);
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sysreg_write(COMPARE, 0);
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evdev->event_handler(evdev);
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return IRQ_HANDLED;
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}
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static struct irqaction timer_irqaction = {
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.handler = timer_interrupt,
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.flags = IRQF_TIMER | IRQF_DISABLED,
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.name = "avr32_comparator",
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};
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static int comparator_next_event(unsigned long delta,
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struct clock_event_device *evdev)
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{
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unsigned long flags;
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raw_local_irq_save(flags);
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/* The time to read COUNT then update COMPARE must be less
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* than the min_delta_ns value for this clockevent source.
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*/
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sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
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raw_local_irq_restore(flags);
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return 0;
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}
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static void comparator_mode(enum clock_event_mode mode,
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struct clock_event_device *evdev)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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pr_debug("%s: start\n", evdev->name);
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/* FALLTHROUGH */
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case CLOCK_EVT_MODE_RESUME:
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cpu_disable_idle_sleep();
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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sysreg_write(COMPARE, 0);
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pr_debug("%s: stop\n", evdev->name);
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cpu_enable_idle_sleep();
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break;
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default:
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BUG();
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}
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}
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static struct clock_event_device comparator = {
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.name = "avr32_comparator",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 16,
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.rating = 50,
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.cpumask = CPU_MASK_CPU0,
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.set_next_event = comparator_next_event,
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.set_mode = comparator_mode,
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};
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void __init time_init(void)
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{
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unsigned long counter_hz;
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int ret;
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/*
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* Make sure we don't get any COMPARE interrupts before we can
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* handle them.
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*/
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sysreg_write(COMPARE, 0);
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xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
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xtime.tv_nsec = 0;
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set_normalized_timespec(&wall_to_monotonic,
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-xtime.tv_sec, -xtime.tv_nsec);
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ret = avr32_hpt_init();
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if (ret) {
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pr_debug("timer: failed setup: %d\n", ret);
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return;
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}
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/* figure rate for counter */
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counter_hz = clk_get_rate(boot_cpu_data.clk);
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counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
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ret = clocksource_register(&clocksource_avr32);
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ret = clocksource_register(&counter);
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if (ret)
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pr_debug("timer: could not register clocksource: %d\n", ret);
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ret = avr32_hpt_start();
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if (ret) {
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pr_debug("timer: failed starting: %d\n", ret);
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return;
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/* setup COMPARE clockevent */
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comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
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comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
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comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
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sysreg_write(COMPARE, 0);
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timer_irqaction.dev_id = &comparator;
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ret = setup_irq(0, &timer_irqaction);
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if (ret)
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pr_debug("timer: could not request IRQ 0: %d\n", ret);
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else {
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clockevents_register_device(&comparator);
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pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
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((counter_hz + 500) / 1000) / 1000,
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((counter_hz + 500) / 1000) % 1000);
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}
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}
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