[PATCH] powerpc: oprofile support for POWER6
POWER6 moves some of the MMCRA bits and also requires some bits to be cleared each PMU interrupt. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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Paul Mackerras
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8eb6c6e3b9
commit
e78dbc800c
@@ -69,6 +69,13 @@ struct cpu_spec {
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/* Processor specific oprofile operations */
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enum powerpc_oprofile_type oprofile_type;
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/* Bit locations inside the mmcra change */
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unsigned long oprofile_mmcra_sihv;
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unsigned long oprofile_mmcra_sipr;
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/* Bits to clear during an oprofile exception */
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unsigned long oprofile_mmcra_clear;
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/* Name of processor class, for the ELF AT_PLATFORM entry */
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char *platform;
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};
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@@ -117,7 +124,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
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#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
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#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
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#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
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#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
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#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
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#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
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#define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
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@@ -134,7 +140,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
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#define CPU_FTR_SMT ASM_CONST(0x0)
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#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
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#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
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#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
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#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
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#define CPU_FTR_PURR ASM_CONST(0x0)
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#endif
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@@ -320,7 +325,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
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CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR)
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CPU_FTR_PURR)
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#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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