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MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2005-12-08 13:00:20 +00:00
committed by
parent 571e0bed85
commit e7958bb90d
4 changed files with 16 additions and 19 deletions
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12
arch/mips/kernel/cpu-probe.c
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@@ -447,10 +447,10 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
isa = (config0 & MIPS_CONF_AT) >> 13; isa = (config0 & MIPS_CONF_AT) >> 13;
switch (isa) { switch (isa) {
case 0: case 0:
c->isa_level = MIPS_CPU_ISA_M32; c->isa_level = MIPS_CPU_ISA_M32R1;
break; break;
case 2: case 2:
c->isa_level = MIPS_CPU_ISA_M64; c->isa_level = MIPS_CPU_ISA_M64R1;
break; break;
default: default:
panic("Unsupported ISA type, cp0.config0.at: %d.", isa); panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
@@ -568,7 +568,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
break; break;
case PRID_IMP_34K: case PRID_IMP_34K:
c->cputype = CPU_34K; c->cputype = CPU_34K;
c->isa_level = MIPS_CPU_ISA_M32; c->isa_level = MIPS_CPU_ISA_M32R1;
break; break;
} }
} }
@@ -647,7 +647,7 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c)
switch (c->processor_id & 0xff00) { switch (c->processor_id & 0xff00) {
case PRID_IMP_PR4450: case PRID_IMP_PR4450:
c->cputype = CPU_PR4450; c->cputype = CPU_PR4450;
c->isa_level = MIPS_CPU_ISA_M32; c->isa_level = MIPS_CPU_ISA_M32R1;
break; break;
default: default:
panic("Unknown Philips Core!"); /* REVISIT: die? */ panic("Unknown Philips Core!"); /* REVISIT: die? */
@@ -690,8 +690,8 @@ __init void cpu_probe(void)
if (c->options & MIPS_CPU_FPU) { if (c->options & MIPS_CPU_FPU) {
c->fpu_id = cpu_get_fpu_id(); c->fpu_id = cpu_get_fpu_id();
if (c->isa_level == MIPS_CPU_ISA_M32 || if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
c->isa_level == MIPS_CPU_ISA_M64) { c->isa_level == MIPS_CPU_ISA_M64R1) {
if (c->fpu_id & MIPS_FPIR_3D) if (c->fpu_id & MIPS_FPIR_3D)
c->ases |= MIPS_ASE_MIPS3D; c->ases |= MIPS_ASE_MIPS3D;
} }

2
arch/mips/kernel/time.c
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@@ -628,7 +628,7 @@ void __init time_init(void)
mips_hpt_init = c0_hpt_init; mips_hpt_init = c0_hpt_init;
} }
if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) || if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32R1) ||
(current_cpu_data.isa_level == MIPS_CPU_ISA_I) || (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
(current_cpu_data.isa_level == MIPS_CPU_ISA_II)) (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
/* /*

4
arch/mips/mm/c-r4k.c
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@@ -1183,8 +1183,8 @@ static void __init setup_scache(void)
if (!sc_present) if (!sc_present)
return; return;
if ((c->isa_level == MIPS_CPU_ISA_M32 || if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
c->isa_level == MIPS_CPU_ISA_M64) && c->isa_level == MIPS_CPU_ISA_M64R1) &&
!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); panic("Dunno how to handle MIPS32 / MIPS64 second level cache");

17
include/asm-mips/cpu.h
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@@ -202,18 +202,15 @@
* ISA Level encodings * ISA Level encodings
* *
*/ */
#define MIPS_CPU_ISA_64BIT 0x00008000
#define MIPS_CPU_ISA_I 0x00000001 #define MIPS_CPU_ISA_I 0x00000001
#define MIPS_CPU_ISA_II 0x00000002 #define MIPS_CPU_ISA_II 0x00000002
#define MIPS_CPU_ISA_III 0x00008003 #define MIPS_CPU_ISA_III (0x00000003 | MIPS_CPU_ISA_64BIT)
#define MIPS_CPU_ISA_IV 0x00008004 #define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT)
#define MIPS_CPU_ISA_V 0x00008005 #define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT)
#define MIPS_CPU_ISA_M32 0x00000020 #define MIPS_CPU_ISA_M32R1 0x00000020
#define MIPS_CPU_ISA_M64 0x00008040 #define MIPS_CPU_ISA_M64R1 (0x00000040 | MIPS_CPU_ISA_64BIT)
/*
* Bit 15 encodes if an ISA level supports 64-bit operations.
*/
#define MIPS_CPU_ISA_64BIT 0x00008000
/* /*
* CPU Option encodings * CPU Option encodings