x86: consolidate SMP code in io_apic.c
Impact: Cleanup Reorganizes the code in arch/x86/kernel/io_apic.c by combining two '#ifdef CONFIG_SMP' regions. In addition to making the code easier to understand the first '#ifdef CONFIG_SMP' region is moved to a location later in the file which will reduce the need for function forward declarations when the code subsequently revised. The only changes other than relocating code to a different position in the file were the removal of the assign_irq_vector() forward declaration which was no longer needed and some line length reduction formatting changes. Signed-off-by: Gary Hade <garyhade@us.ibm.com> Cc: lcm@us.ibm.com LKML-Reference: <20090408210725.GC11159@us.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Gary Hade
Ingo Molnar
@@ -518,120 +518,6 @@ static void ioapic_mask_entry(int apic, int pin)
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spin_unlock_irqrestore(&ioapic_lock, flags);
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spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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}
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#ifdef CONFIG_SMP
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static void send_cleanup_vector(struct irq_cfg *cfg)
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{
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cpumask_var_t cleanup_mask;
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if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
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unsigned int i;
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cfg->move_cleanup_count = 0;
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for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
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cfg->move_cleanup_count++;
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for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
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apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
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} else {
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cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
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cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
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apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
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free_cpumask_var(cleanup_mask);
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}
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cfg->move_in_progress = 0;
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}
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static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
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{
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int apic, pin;
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struct irq_pin_list *entry;
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u8 vector = cfg->vector;
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entry = cfg->irq_2_pin;
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for (;;) {
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unsigned int reg;
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if (!entry)
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break;
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apic = entry->apic;
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pin = entry->pin;
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/*
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* With interrupt-remapping, destination information comes
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* from interrupt-remapping table entry.
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*/
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if (!irq_remapped(irq))
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io_apic_write(apic, 0x11 + pin*2, dest);
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reg = io_apic_read(apic, 0x10 + pin*2);
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reg &= ~IO_APIC_REDIR_VECTOR_MASK;
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reg |= vector;
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io_apic_modify(apic, 0x10 + pin*2, reg);
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if (!entry->next)
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break;
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entry = entry->next;
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}
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}
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static int
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assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
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/*
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* Either sets desc->affinity to a valid value, and returns
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* ->cpu_mask_to_apicid of that, or returns BAD_APICID and
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* leaves desc->affinity untouched.
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*/
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static unsigned int
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set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
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{
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struct irq_cfg *cfg;
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unsigned int irq;
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if (!cpumask_intersects(mask, cpu_online_mask))
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return BAD_APICID;
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irq = desc->irq;
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cfg = desc->chip_data;
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if (assign_irq_vector(irq, cfg, mask))
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return BAD_APICID;
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/* check that before desc->addinity get updated */
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set_extra_move_desc(desc, mask);
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cpumask_copy(desc->affinity, mask);
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return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
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}
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static void
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set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
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{
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struct irq_cfg *cfg;
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unsigned long flags;
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unsigned int dest;
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unsigned int irq;
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irq = desc->irq;
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cfg = desc->chip_data;
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spin_lock_irqsave(&ioapic_lock, flags);
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dest = set_desc_affinity(desc, mask);
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if (dest != BAD_APICID) {
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/* Only the high 8 bits are valid. */
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dest = SET_APIC_LOGICAL_ID(dest);
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__target_IO_APIC_irq(irq, dest, cfg);
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}
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spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void
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set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
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{
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struct irq_desc *desc;
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desc = irq_to_desc(irq);
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set_ioapic_affinity_irq_desc(desc, mask);
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}
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#endif /* CONFIG_SMP */
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/*
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/*
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* The common case is 1:1 IRQ<->pin mappings. Sometimes there are
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* The common case is 1:1 IRQ<->pin mappings. Sometimes there are
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* shared ISA-space IRQs, so we have to support them. We are super
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* shared ISA-space IRQs, so we have to support them. We are super
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@@ -2360,6 +2246,115 @@ static int ioapic_retrigger_irq(unsigned int irq)
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*/
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*/
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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static void send_cleanup_vector(struct irq_cfg *cfg)
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{
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cpumask_var_t cleanup_mask;
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if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
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unsigned int i;
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cfg->move_cleanup_count = 0;
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for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
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cfg->move_cleanup_count++;
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for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
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apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
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} else {
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cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
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cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
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apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
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free_cpumask_var(cleanup_mask);
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}
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cfg->move_in_progress = 0;
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}
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static void
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__target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
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{
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int apic, pin;
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struct irq_pin_list *entry;
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u8 vector = cfg->vector;
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entry = cfg->irq_2_pin;
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for (;;) {
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unsigned int reg;
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if (!entry)
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break;
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apic = entry->apic;
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pin = entry->pin;
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/*
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* With interrupt-remapping, destination information comes
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* from interrupt-remapping table entry.
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*/
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if (!irq_remapped(irq))
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io_apic_write(apic, 0x11 + pin*2, dest);
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reg = io_apic_read(apic, 0x10 + pin*2);
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reg &= ~IO_APIC_REDIR_VECTOR_MASK;
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reg |= vector;
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io_apic_modify(apic, 0x10 + pin*2, reg);
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if (!entry->next)
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break;
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entry = entry->next;
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}
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}
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/*
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* Either sets desc->affinity to a valid value, and returns
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* ->cpu_mask_to_apicid of that, or returns BAD_APICID and
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* leaves desc->affinity untouched.
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*/
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static unsigned int
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set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
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{
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struct irq_cfg *cfg;
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unsigned int irq;
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if (!cpumask_intersects(mask, cpu_online_mask))
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return BAD_APICID;
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irq = desc->irq;
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cfg = desc->chip_data;
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if (assign_irq_vector(irq, cfg, mask))
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return BAD_APICID;
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/* check that before desc->addinity get updated */
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set_extra_move_desc(desc, mask);
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cpumask_copy(desc->affinity, mask);
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return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
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}
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static void
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set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
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{
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struct irq_cfg *cfg;
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unsigned long flags;
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unsigned int dest;
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unsigned int irq;
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irq = desc->irq;
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cfg = desc->chip_data;
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spin_lock_irqsave(&ioapic_lock, flags);
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dest = set_desc_affinity(desc, mask);
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if (dest != BAD_APICID) {
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/* Only the high 8 bits are valid. */
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dest = SET_APIC_LOGICAL_ID(dest);
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__target_IO_APIC_irq(irq, dest, cfg);
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}
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spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void
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set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
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{
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struct irq_desc *desc;
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desc = irq_to_desc(irq);
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set_ioapic_affinity_irq_desc(desc, mask);
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}
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#ifdef CONFIG_INTR_REMAP
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#ifdef CONFIG_INTR_REMAP
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