fsldma: move related helper functions near each other
This is a purely cosmetic cleanup. It is nice to have related functions right next to each other in the code. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
@@ -39,33 +39,9 @@
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static const char msg_ld_oom[] = "No free memory for link descriptor\n";
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static const char msg_ld_oom[] = "No free memory for link descriptor\n";
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static void dma_init(struct fsldma_chan *chan)
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/*
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{
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* Register Helpers
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/* Reset the channel */
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*/
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DMA_OUT(chan, &chan->regs->mr, 0, 32);
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switch (chan->feature & FSL_DMA_IP_MASK) {
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case FSL_DMA_IP_85XX:
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/* Set the channel to below modes:
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* EIE - Error interrupt enable
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* EOSIE - End of segments interrupt enable (basic mode)
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* EOLNIE - End of links interrupt enable
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* BWC - Bandwidth sharing among channels
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*/
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DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
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| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
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| FSL_DMA_MR_EOSIE, 32);
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break;
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case FSL_DMA_IP_83XX:
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/* Set the channel to below modes:
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* EOTIE - End-of-transfer interrupt enable
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* PRC_RM - PCI read multiple
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*/
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DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
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| FSL_DMA_MR_PRC_RM, 32);
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break;
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}
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}
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static void set_sr(struct fsldma_chan *chan, u32 val)
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static void set_sr(struct fsldma_chan *chan, u32 val)
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{
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{
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@@ -77,6 +53,30 @@ static u32 get_sr(struct fsldma_chan *chan)
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return DMA_IN(chan, &chan->regs->sr, 32);
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return DMA_IN(chan, &chan->regs->sr, 32);
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}
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}
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static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
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{
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DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
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}
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static dma_addr_t get_cdar(struct fsldma_chan *chan)
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{
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return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
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}
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static dma_addr_t get_ndar(struct fsldma_chan *chan)
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{
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return DMA_IN(chan, &chan->regs->ndar, 64);
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}
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static u32 get_bcr(struct fsldma_chan *chan)
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{
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return DMA_IN(chan, &chan->regs->bcr, 32);
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}
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/*
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* Descriptor Helpers
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*/
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static void set_desc_cnt(struct fsldma_chan *chan,
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static void set_desc_cnt(struct fsldma_chan *chan,
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struct fsl_dma_ld_hw *hw, u32 count)
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struct fsl_dma_ld_hw *hw, u32 count)
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{
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{
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@@ -113,24 +113,49 @@ static void set_desc_next(struct fsldma_chan *chan,
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hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
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hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
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}
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}
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static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
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static void set_ld_eol(struct fsldma_chan *chan,
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struct fsl_desc_sw *desc)
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{
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{
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DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
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u64 snoop_bits;
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snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
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? FSL_DMA_SNEN : 0;
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desc->hw.next_ln_addr = CPU_TO_DMA(chan,
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DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
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| snoop_bits, 64);
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}
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}
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static dma_addr_t get_cdar(struct fsldma_chan *chan)
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/*
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{
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* DMA Engine Hardware Control Helpers
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return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
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*/
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}
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static dma_addr_t get_ndar(struct fsldma_chan *chan)
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static void dma_init(struct fsldma_chan *chan)
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{
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{
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return DMA_IN(chan, &chan->regs->ndar, 64);
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/* Reset the channel */
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}
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DMA_OUT(chan, &chan->regs->mr, 0, 32);
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static u32 get_bcr(struct fsldma_chan *chan)
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switch (chan->feature & FSL_DMA_IP_MASK) {
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{
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case FSL_DMA_IP_85XX:
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return DMA_IN(chan, &chan->regs->bcr, 32);
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/* Set the channel to below modes:
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* EIE - Error interrupt enable
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* EOSIE - End of segments interrupt enable (basic mode)
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* EOLNIE - End of links interrupt enable
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* BWC - Bandwidth sharing among channels
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*/
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DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
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| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
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| FSL_DMA_MR_EOSIE, 32);
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break;
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case FSL_DMA_IP_83XX:
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/* Set the channel to below modes:
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* EOTIE - End-of-transfer interrupt enable
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* PRC_RM - PCI read multiple
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*/
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DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
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| FSL_DMA_MR_PRC_RM, 32);
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break;
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}
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}
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}
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static int dma_is_idle(struct fsldma_chan *chan)
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static int dma_is_idle(struct fsldma_chan *chan)
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@@ -185,19 +210,6 @@ static void dma_halt(struct fsldma_chan *chan)
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dev_err(chan->dev, "DMA halt timeout!\n");
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dev_err(chan->dev, "DMA halt timeout!\n");
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}
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}
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static void set_ld_eol(struct fsldma_chan *chan,
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struct fsl_desc_sw *desc)
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{
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u64 snoop_bits;
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snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
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? FSL_DMA_SNEN : 0;
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desc->hw.next_ln_addr = CPU_TO_DMA(chan,
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DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
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| snoop_bits, 64);
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}
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/**
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/**
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* fsl_chan_set_src_loop_size - Set source address hold transfer size
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* fsl_chan_set_src_loop_size - Set source address hold transfer size
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* @chan : Freescale DMA channel
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* @chan : Freescale DMA channel
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